Testing for Transistor Aging

Transistor aging results in circuit delay degradation over time,and is a growing concern for future systems. On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing.Effective circuit failure prediction requires very thorough testing to estimate the amount of aging in various parts of a large design during system operation. This paper introduces such testing techniques. Results on large designs demonstrate the practicality and effectiveness of presented techniques.

[1]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[2]  Yu Cao,et al.  Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[3]  Jeff Rearick,et al.  Empirical Validation of Yield Recovery Using Idle-Cycle Insertion , 2007, IEEE Design & Test of Computers.

[4]  Radu Marculescu,et al.  Probabilistic modeling of dependencies during switching activity analysis , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Jeff Rearick,et al.  Calibrating clock stretch during AC scan testing , 2005, IEEE International Conference on Test, 2005..

[6]  Subhasish Mitra Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges , 2008, 2008 Design, Automation and Test in Europe.

[7]  Randy L. Haupt,et al.  Practical Genetic Algorithms , 1998 .

[8]  Sudhakar M. Reddy,et al.  On path selection in combinational logic circuits , 1988, DAC '88.

[9]  David Blaauw,et al.  Statistical Timing Analysis: From Basic Principles to State of the Art , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  John H. Holland,et al.  Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence , 1992 .

[11]  Janak H. Patel,et al.  Finding a small set of longest testable paths that cover every gate , 2002, Proceedings. International Test Conference.

[12]  Kwang-Ting Cheng,et al.  Critical path selection for delay fault testing based upon a statistical timing model , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Sharad Malik,et al.  Statistical timing analysis of combinational logic circuits , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Sudhakar M. Reddy,et al.  Long and short covering edges in combination logic circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Farzad Nekoogar Timing Verification of Application-Specific Integrated Circuits (Asics) , 1999 .

[16]  Kelin Kuhn,et al.  Managing Process Variation in Intel’s 45nm CMOS Technology , 2008 .

[17]  Edward J. McCluskey,et al.  DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS , 1991, 1991, Proceedings. International Test Conference.

[18]  David Hung-Chang Du,et al.  Efficient Algorithms for Extracting the K Most Critical Paths in Timing Analysis , 1989, 26th ACM/IEEE Design Automation Conference.

[19]  N. Ahmed,et al.  A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[20]  Janak H. Patel,et al.  Fast identification of untestable delay faults using implications , 1997, ICCAD 1997.

[21]  Luciano Lavagno,et al.  Electronic Design Automation for Integrated Circuits Handbook , 2006 .

[22]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[23]  Ananta K. Majhi,et al.  On hazard-free patterns for fine-delay fault testing , 2004 .

[24]  J. Hicks 45nm Transistor Reliability , 2008 .

[25]  Masami Murakata,et al.  Switching activity analysis for sequential circuits using Boolean approximation method , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[26]  Spyros Tragoudas,et al.  A critical path selection method for delay testing , 2004, 2004 International Conferce on Test.

[27]  L. Wang,et al.  Experience in critical path selection for deep sub-micron delay test and timing validation , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[28]  S. Natarajan,et al.  Impact of negative bias temperature instability on digital circuit reliability , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[29]  Ioannis G. Tollis,et al.  Improved Techniques for Estimating Signal Probabilities , 1989, IEEE Trans. Computers.

[30]  Rahim Kasim,et al.  Reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging , 2009, 2009 IEEE International Reliability Physics Symposium.

[31]  Masami Murakata,et al.  Switching activity analysis for sequential circuits using Boolean approximation method , 1996, ISLPED.

[32]  Hiroaki Inoue,et al.  VAST: Virtualization-Assisted Concurrent Autonomous Self-Test , 2008, 2008 IEEE International Test Conference.

[33]  Edward J. McCluskey,et al.  Probabilistic Treatment of General Combinational Networks , 1975, IEEE Transactions on Computers.

[34]  Shekhar Y. Borkar,et al.  Electronics beyond nano-scale CMOS , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[35]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[36]  Irith Pomeranz,et al.  A method for identifying robust dependent and functionally unsensitizable paths , 1997, Proceedings Tenth International Conference on VLSI Design.

[37]  Seiichiro Tani,et al.  Efficient Path Selection for Delay Testing Based on Path Clustering , 1999, J. Electron. Test..

[38]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[39]  Spyros Tragoudas,et al.  Efficient identification of (critical) testable path delay faults using decision diagrams , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[40]  Yu Cao,et al.  An efficient method to identify critical gates under circuit aging , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[41]  Seiichiro Tani,et al.  Efficient path selection for delay testing based on partial path evaluation , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[42]  Subhasish Mitra,et al.  CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns , 2008, 2008 Design, Automation and Test in Europe.

[43]  Bo Yang,et al.  Optimized Circuit Failure Prediction for Aging: Practicality and Promise , 2008, 2008 IEEE International Test Conference.

[44]  Irith Pomeranz,et al.  Selection of potentially testable path delay faults for test generation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[45]  Stephen P. Boyd,et al.  An Efficient Method for Large-Scale Gate Sizing , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[46]  Mark Mohammad Tehranipoor,et al.  Timing-based delay test for screening small delay defects , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[47]  Chang Seo Park,et al.  Mechanism of Electron Trapping and Characteristics of Traps in $\hbox{HfO}_{2}$ Gate Stacks , 2007, IEEE Transactions on Device and Materials Reliability.