RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to $(8n+1)$ -bit

In the last years, investigation on residue number systems (RNS) has targeted parallelism and larger dynamic ranges. In this paper, we start from the moduli set {2n,2n-1,2n+1,2n-2(n+1)/2+1,2n+2(n+1)/2+1} , with an equivalent 5n -bit dynamic range, and propose horizontal and vertical extensions in order to improve the parallelism and increase the dynamic range. The vertical extensions increase the value of the power-of-2 modulus in the five-moduli set. With the horizontal extensions, new six channel sets are allowed by introducing the 2n+1+1 or 2n-1+1 moduli. This paper proposes methods to design memoryless reverse converters for the proposed moduli sets with large dynamic ranges, up to (8n+1)-bit. Due to the complexity of the reverse conversion, both the Chinese Remainder Theorem and the Mixed Radix Conversion are applied in the proposed methods to derive efficient reverse converters. Experimental results suggest that the proposed vertical extensions allow to reduce the area-delay-product up to 1.34 times in comparison with the related state-of-the-art. The horizontal extensions allow larger and more balanced moduli sets, resulting in an improvement of the RNS arithmetic computation, at the cost of lower reverse conversion performance.

[1]  Uwe Meyer-Baese,et al.  High performance, reduced complexity programmable RNS-FPL merged FIR filters , 2002 .

[2]  P. V. Ananda Mohan,et al.  RNS-to-Binary Converters for Two Four-Moduli Sets $\{2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}-1\}$ and $\{2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}+1\}$ , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  A. Omondi,et al.  Residue Number Systems: Theory and Implementation , 2007 .

[4]  Yuke Wang.  Residue-to-binary converters based on new Chinese remainder theorems , 2000 .

[5]  Ahmad A. Hiasat,et al.  VLSI implementation of new arithmetic residue to binary decoders , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Chip-Hong Chang,et al.  An Efficient Reverse Converter for the 4-Moduli Set , , , Based on the New , 2003 .

[7]  M. Omair Ahmad,et al.  A high-speed residue-to-binary converter and a scheme for its VLSI implementation , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[8]  Graham A. Jullien,et al.  An efficient tree architecture for modulo 2n+1 multiplication , 1996, J. VLSI Signal Process..

[9]  A. Lloris,et al.  A RNS-based matrix-vector-multiply FCT architecture for DCT computation , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[10]  P. V. Ananda Mohan,et al.  RNS-To-Binary Converter for a New Three-Moduli Set $\{2^{{n}+1}-1,2^{n},2^{n}-1\}$ , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Laurent-Stéphane Didier,et al.  A Generalization of a Fast RNS Conversion for a New 4-Modulus Base , 2009 .

[12]  Chip-Hong Chang,et al.  Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1, 2n, 2n+1} Based RNS , 2012, IEEE Trans. Circuits Syst. I Regul. Pap..

[13]  Leonel Sousa,et al.  Elliptic Curve point multiplication on GPUs , 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

[14]  L. Sousa,et al.  {\text{\{ 2}}^{\text{n}} + 1,2^{n + k} ,2^n - 1\}: A New RNS Moduli Set Extension , 2004 .

[15]  Haridimos T. Vergos,et al.  Efficient modulo 2n + 1 multi-operand adders , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[16]  Thanos Stouraitis,et al.  Design of a balanced 8-modulus RNS , 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

[17]  Reto Zimmermann,et al.  Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[18]  Thanos Stouraitis,et al.  Grouped-moduli residue number systems for fast signal processing , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[19]  Chip-Hong Chang,et al.  An efficient reverse converter for the 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup 2n/ + 1} based on the new Chinese remainder theorem , 2003 .

[20]  Chip-Hong Chang,et al.  Efficient reverse converters for four-moduli sets { 2n−1, 2n, 2n+1, 2n+1−1} and {2n−1, 2n, 2n+1, 2n−1−1} , 2005 .

[21]  Richard I. Tanaka,et al.  Residue arithmetic and its applications to computer technology , 1967 .

[22]  Jonathan P. Sorenson.  Two Fast GCD Algorithms , 1994, J. Algorithms.

[23]  Ricardo Chaves,et al.  {2/sup n/ + 1, 2/sup n+k/, 2/sup n/ - 1} : a new RNS moduli set extension , 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

[24]  Yong Liu,et al.  Moduli Set Selection and Cost Estimation for RNS-Based FIR Filter and Filter Bank Design , 2004, Des. Autom. Embed. Syst..

[25]  L. Sousa,et al.  MRC-Based RNS Reverse Converters for the Four-Moduli Sets $\{2^{n} + 1, 2^{n} - 1, 2^{n}, 2^{2n + 1} - 1\}$ and $ \{2^{n} + 1, 2^{n} - 1, 2^{2n}, 2^{2n + 1} - 1\}$ , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[26]  Behrooz Parhami,et al.  On equivalences and fair comparisons among residue number systems with special moduli , 2010, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers.

[27]  D. H. Jacobsohn,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[28]  Ming-Hwa Sheu,et al.  An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3, 2n+1, 2n-1, 2n+3) , 2004, IEEE Trans. Circuits Syst. II Express Briefs.

[29]  Leonel Sousa,et al.  Corrections to “MRC-Based RNS Reverse Converters for the Four-Moduli Sets and ” [Apr 12 244-248] , 2012 .

[30]  Alexander Skavantzos,et al.  Implementation issues of the two-level residue number system with pairs of conjugate moduli , 1999, IEEE Trans. Signal Process..

[31]  A. Skavantzos,et al.  Novel residue arithmetic processors for high speed digital signal processing , 1998, Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284).

[32]  Omid Kavehei,et al.  Efficient Reverse Converter Designs for the New 4-Moduli Sets $\{2^{n} -1, 2^{n}, 2^{n} +1, 2^{2n + 1}-1\}$ and $\{2^{n} -1, 2^{n} +1, 2^{2n}, 2^{2n} +1\}$ Based on New CRTs , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  Alexander Skavantzos,et al.  An efficient residue to weighted converter for a new residue number system , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[34]  Chip-Hong Chang,et al.  A Residue-to-Binary Converter for a New Five-Moduli Set , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[35]  Stanislaw J. Piestrak.  Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders , 1994, IEEE Trans. Computers.

[36]  Keivan Navi,et al.  A new high dynamic range moduli set with efficient reverse converter , 2008, Comput. Math. Appl..

[37]  Keivan Navi,et al.  An improved reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1} , 2008, IEICE Electron. Express.

[38]  A. Skavantzos,et al.  New efficient RNS-to-weighted decoders for conjugate-pair-moduli residue number systems , 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).

[39]  Laurent Imbert,et al.  a full RNS implementation of RSA , 2004, IEEE Transactions on Computers.

[40]  B. Cao,et al.  Efficient reverse converters for four-moduli sets {2^n-1, 2^n, 2^n+1, 2^n^+^1-1} and {2^n-1, 2^n, 2^n+1, 2^n^-^1-1} , 2005 .