Intelligence implementation on silicon based on four-terminal device electronics

We propose the concept of a high-functionality "four-terminal device" which surpasses the three-terminal devices like MOSFET's and bipolar transistors in the ability of current control functions. The enhanced functionality at the very elemental transistor level is most essential to create human-like intelligence at system levels. The neuron MOSFET (/spl nu/MOS), a multiple-input-terminal floating-gate device, is taken as an example of a four-terminal device, and the implementation of intelligent electronic circuits on Si is demonstrated. The binary-multivalue-analog merged algorithm conducted by /spl nu/MOS circuits is a key to realizing highly flexible computation while assuring the noise immune feature of binary digital computation.

[1]  Tadashi Shibata,et al.  Real-time reconfigurable logic circuits using neuron MOS transistors , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Tadashi Shibata,et al.  The Concept of Four-Terminal Devices and Its Significance in the Implementation of Intelligent Integrated Circuits , 1994 .

[3]  Tadahiro Ohmi,et al.  A self-learning neural-network LSI using neuron MOSFETs , 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

[4]  Tadashi Shibata,et al.  Neuron MOS winner-take-all circuit and its application to associative memory , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  Tadashi Shibata,et al.  A neuron-MOS neural network using self-learning-compatible synapse circuits , 1995, IEEE J. Solid State Circuits.

[6]  Tadashi Shibata,et al.  Hardware-Oriented Learning Algorithm Implemented on Silicon Using Neuron MOS Technology , 1994 .

[7]  W. Pitts,et al.  A Logical Calculus of the Ideas Immanent in Nervous Activity (1943) , 2021, Ideas That Created the Future.

[8]  Tadashi Shibata,et al.  Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation , 1993 .

[9]  Tadahiro Ohmi,et al.  An intelligent MOS transistor featuring gate-level weighted sum and threshold operations , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[10]  Tadashi Shibata,et al.  Neuron-MOS multiple-valued memory technology for intelligent data processing , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[11]  T. Ohmi ULSI reliability through ultraclean processing , 1993, Proc. IEEE.

[12]  T. Ohmi,et al.  Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[13]  T. Ohmi,et al.  Hardware-backpropagation learning of neuron MOS neural networks , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[14]  Tadahiro Ohmi,et al.  Neuron MOS binary-logic integrated circuits. II. Simplifying techniques of circuit configuration and their practical applications , 1993 .

[15]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[16]  Tadashi Shibata,et al.  Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[17]  Tadashi Shibata,et al.  An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning Neuron-MOS neural networks , 1993 .