Heavy Ion Testing and 3-D Simulations of Multiple Cell Upset in 65 nm Standard SRAMs

Heavy ions experiments are carried out on commercial 90 nm and 65 nm SRAMs. The contribution of single and multiple cell upsets (MCUs) are discussed as a function of the LET for different memory cell areas and for triple well usage. Once again, well engineering plays a key role on MCU and SEE response of SRAM. Full 3-D TCAD simulations investigate the occurrence of parasitic bipolar effect.

[1]  G. Gasiot,et al.  Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering , 2007, IEEE Transactions on Nuclear Science.

[2]  R. Harboe-Sorensen,et al.  Multiple-Bit Upset Analysis in 90 nm SRAMs: Heavy Ions Testing and 3D Simulations , 2007, IEEE Transactions on Nuclear Science.

[3]  G. Gasiot,et al.  Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65 nm CMOS Technology , 2006, IEEE Transactions on Nuclear Science.

[4]  G. Gasiot,et al.  Impacts of front-end and middle-end process modifications on terrestrial soft error rate , 2005, IEEE Transactions on Device and Materials Reliability.

[5]  P. Graham,et al.  Radiation-induced multi-bit upsets in SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.

[6]  H. Puchner,et al.  Alpha-particle SEU performance of SRAM with triple well , 2004, IEEE Transactions on Nuclear Science.

[7]  R. Harboe-Sorensen,et al.  High penetration heavy tons at the RADEF test site , 2003, Proceedings of the 7th European Conference on Radiation and Its Effects on Components and Systems, 2003. RADECS 2003..

[8]  Gilles Gasiot,et al.  Comparisons of soft error rate for SRAMs in commercial SOI and bulk below the 130-nm technology node , 2003 .

[9]  K. Osada,et al.  Cosmic-ray multi-error immunity for SRAM, based on analysis of the parasitic bipolar effect , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).