A 125-ps 8–18-GHz CMOS Integrated Delay Circuit

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125- and 3.9-ps delay resolution, designed and fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second-, fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2–23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8–18 GHz. Input and output reflection coefficients are better than −11 dB for the delay chain including the effect of RF bondwires and pads. The fabricated chip occupies an area of <inline-formula> <tex-math notation="LaTeX">$2.0\times 1.0$ </tex-math></inline-formula> mm<sup>2</sup> and has no dc power consumption.

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