Simulation and Verification of VITAL-based FPGA System

Verification of digital circuits is a significant issue because the fabrication process progresses rapidly from very large scale integrated circuit to system on chip.Traditional method of design verification is prototyping.It's obviously expensive and can not be adapted to the reduced time to go on the market when developing FPGA - based prototype again.Simulation attempts to create a virtual prototype by collecting information about the components,it has the virtue of independent technology and easier debugging.The paper introduced VITAL and the way to model component with VITAL.Research status of board - level verification of FPGA and its prerequisite and procedure are discussed,and experiment results show the validity of the method.The work plays a part in generalizing domestic VITAL - based board - level verification of FPGA.