On the infeasibility of analysing worst-case dynamic energy

In this paper we study the sources of dynamic energy during the execution of software on microprocessors suited for the Internet of Things (IoT) domain. Estimating the energy consumed by executing software is typically achieved by determining the most costly path through the program according to some energy model of the processor. Few models, however, adequately tackle the matter of dynamic energy caused by operand data. We find that the contribution of operand data to overall energy can be significant, prove that finding the worst-case input data is NP-hard, and further, that it cannot be estimated to any useful factor. Our work shows that accurate worst-case analysis of data dependent energy is infeasible, and that other techniques for energy estimation should be considered.

[1]  Xianfeng Li,et al.  Estimating the Worst-Case Energy Consumption of Embedded Software , 2006, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06).

[2]  Per Stenström,et al.  Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[3]  Michael S. Hsiao,et al.  K2: an estimator for peak sustainable power of VLSI circuits , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[4]  David M. Brooks,et al.  Energy characterization and instruction-level energy model of Intel's Xeon Phi processor , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[5]  Kerstin Eder,et al.  Data dependent energy modelling: A worst case perspective , 2015, ArXiv.

[6]  Manuel V. Hermenegildo,et al.  Energy Consumption Analysis of Programs Based on XMOS ISA-Level Models , 2013, LOPSTR.

[7]  Kerstin Eder,et al.  A high-level model of embedded flash energy consumption , 2014, 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

[8]  Neil W. Bergmann,et al.  Performance evaluation of asynchronous logic pipelines with data dependent processing delays , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[9]  Kerstin Eder,et al.  Static analysis of energy consumption for LLVM IR programs , 2014, SCOPES.

[10]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[11]  Sourav Roy,et al.  Estimation of energy consumed by software in processor caches , 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[12]  Kerstin Eder,et al.  On the Value and Limits of Multi-level Energy Consumption Static Analysis for Deeply Embedded Single and Multi-threaded Programs , 2015, ArXiv.

[13]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Anantha Chandrakasan,et al.  Energy aware software , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[15]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, Proceedings of 9th International Conference on VLSI Design.

[16]  Paulo Francisco Butzen,et al.  Leakage Current in Sub-Micrometer CMOS Gates , 2008 .

[17]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, ICCAD.

[18]  Vijay V. Vazirani,et al.  Approximation Algorithms , 2001, Springer Berlin Heidelberg.

[19]  Kerstin Eder,et al.  Energy Modeling of Software for a Hardware Multithreaded Embedded Microprocessor , 2015, ACM Trans. Embed. Comput. Syst..

[20]  Annalisa Bossi Logic-Based Program Synthesis and Transformation , 1999, Lecture Notes in Computer Science.

[21]  Peter Kulchyski and , 2015 .

[22]  Paulo F. Flores,et al.  Generating Realistic Stimuli for Accurate Power Grid Analysis , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[23]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[24]  Arlindo L. Oliveira,et al.  On The Complexity Of Power Estimation Problems , 2007 .

[25]  Mahmut T. Kandemir,et al.  Instruction Scheduling for Low Power , 2004, J. VLSI Signal Process..

[26]  Kamran Rahmani,et al.  Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis , 2015, 2015 28th International Conference on VLSI Design.

[27]  Soontae Kim,et al.  DRAM energy reduction by prefetching-based memory traffic clustering , 2011, GLSVLSI '11.

[28]  Lothar Thiele,et al.  Design for Timing Predictability , 2004, Real-Time Systems.

[29]  Tobias Distler,et al.  Worst-Case Energy Consumption Analysis for Energy-Constrained Embedded Systems , 2015, 2015 27th Euromicro Conference on Real-Time Systems.

[30]  Christoforos E. Kozyrakis,et al.  Understanding sources of inefficiency in general-purpose chips , 2010, ISCA.

[31]  David A. Patterson,et al.  Computer Architecture, Fifth Edition: A Quantitative Approach , 2011 .

[32]  Gernot Heiser,et al.  An Analysis of Power Consumption in a Smartphone , 2010, USENIX Annual Technical Conference.

[33]  Peter Marwedel,et al.  An Accurate and Fine Grain Instruction-Level Energy Model Supporting Software Optimizations , 2007 .

[34]  Toby Walsh,et al.  Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications , 2009 .

[35]  Christoforos E. Kozyrakis,et al.  A Comparison of High-Level Full-System Power Models , 2008, HotPower.

[36]  David S. Johnson,et al.  Approximation algorithms for combinatorial problems , 1973, STOC.

[37]  David May,et al.  The XMOS XS1 Architecture , 2009 .

[38]  Vincenzo Catania,et al.  An Instruction-Level Power Analysis Model with Data Dependency , 2001, VLSI Design.