eDRAM-based Tiered-Reliability Memory with applications to low-power frame buffers
暂无分享,去创建一个
[1] Dan Grossman,et al. EnerJ: approximate data types for safe and general low-power computation , 2011, PLDI '11.
[2] W. Marsden. I and J , 2012 .
[3] Song Liu,et al. Flikker: saving DRAM refresh-power through critical data partitioning , 2011, ASPLOS XVI.
[4] Marios C. Papaefthymiou,et al. Block-based multiperiod dynamic memory design for low data-retention power , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[5] Hsien-Hsin S. Lee,et al. Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[6] Gu-Yeon Wei,et al. Process Variation Tolerant 3T1D-Based Cache Architectures , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[7] Philip G. Emma,et al. Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications , 2008, IEEE Micro.
[8] WilkersonChris,et al. Reducing cache power with low-cost, multi-bit error-correcting codes , 2010 .
[9] Ahmed M. Eltawil,et al. Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM , 2011, 2011 IEEE 6th International Design and Test Workshop (IDT).
[10] Travis E. Oliphant,et al. Guide to NumPy , 2015 .
[11] Richard Veras,et al. RAIDR: Retention-aware intelligent DRAM refresh , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[12] Eero P. Simoncelli,et al. Image quality assessment: from error visibility to structural similarity , 2004, IEEE Transactions on Image Processing.
[13] H. Fujiwara,et al. Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential — , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.
[14] Kaushik Roy,et al. A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications , 2011, IEEE Transactions on Circuits and Systems for Video Technology.
[15] Jongsun Park,et al. Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[16] Nikil D. Dutt,et al. AVid: Annotation driven video decoding for hybrid memories , 2012, 2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia.
[17] Yao Lu,et al. Compiler assisted dynamic register file in GPGPU , 2013, International Symposium on Low Power Electronics and Design (ISLPED).
[18] P. Cochat,et al. Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.
[19] Wei Wu,et al. Reducing cache power with low-cost, multi-bit error-correcting codes , 2010, ISCA.
[20] Na Gong,et al. Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.
[21] Bruce Jacob,et al. Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).
[22] Jason Schlessman,et al. Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[23] Kaushik Roy,et al. TFT-LCD application specific low power SRAM using charge-recycling technique , 2005, Sixth international symposium on quality electronic design (isqed'05).
[24] Richard E. Matick,et al. A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[25] Gernot Heiser,et al. An Analysis of Power Consumption in a Smartphone , 2010, USENIX Annual Technical Conference.
[26] Dhiraj K. Pradhan,et al. A soft error robust and power aware memory design , 2007, SBCCI '07.
[27] Eric Rotenberg,et al. Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..
[28] W. Luk,et al. A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..
[29] Naehyuck Chang,et al. A compressed frame buffer to reduce display power consumption in mobile systems , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
[30] Alexander W. Min,et al. A hybrid display frame buffer architecture for energy efficient display subsystems , 2013, International Symposium on Low Power Electronics and Design (ISLPED).