A 2.4 GS/s Time Interleaved ADC with 76 dB SFDR in 0.18 μm BiCMOS

A time interleaved pipeline analog-to-digital converter (ADC) in 0.18 μm BiCMOS process is proposed. Such an ADC consists of the two same channels, each with 4 interleaved sub-ADCs. In each channel, a single track/hold (T/ H) is integrated in front of the 4 lanes, thereby avoiding timing skew among lanes. A power efficient clock buffer using bipolar transistors is presented to generate the original clock signal. Timing system is also adopted to align the phases of ADC lanes with the T/H. The two channels can also be further interleaved, with timing skew between them trimmed by a capacitor array. A trimming scheme with current-steering digital-to-analog converter (DAC) is proposed to remove the spur brought by the gain error mismatch between the 2 channels. The operation mode is controlled by an analog mux with bootstrapped switches. The simulation results show that in the interleaved mode, the SFDR and SNDR can achieve 76 dB and 60 dB @ 2.4GS/s, respectively. The power of the ADC core with 2 channels is 1360 m W, thus achieving 695 Fj/Conv Walden figure of merit (FOM).