iWarp multicomputer with an embedded switching network
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Abstract This brief describes the iWarp multicomputer architecture. The two components of each iWarp cell, a 20 MFLOPS and 20 MIPS computation agent and a 320 Mbyte s−1 communication agent for interfacing with other cells, can operate independently, but their location on a single chip allows for tight coupling. A variety of communication methods are supported by iWarp.
[1] Monica S. Lam,et al. Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor , 1989, ASPLOS.
[2] H. T. Kung,et al. The Warp Computer: Architecture, Implementation, and Performance , 1987, IEEE Transactions on Computers.
[3] Monica Sin-Ling Lam,et al. A Systolic Array Optimizing Compiler , 1989 .