Dynamic noise analysis in precharge-evaluate circuits

A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit is cross-talk, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified by HSPICE simulation on DOMINO gates. A tool is also developed to obtain static and dynamic noise-margins at various points in the circuit. Dynamic noise-margins are translated into maximum allowable coupling capacitances between the pairs of nets for precharge-evaluate logic circuits. An accurate estimate of dynamic noise-margin and coupling coefficient bounds will allow improvement of the circuits in terms of robustness.

[1]  Andrew B. Kahng,et al.  Interconnect tuning strategies for high-performance ICs , 1998, DATE.

[2]  Dennis Sylvester,et al.  Interconnect scaling: signal integrity and performance in future high-speed CMOS designs , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[3]  Dinesh Somasekhar,et al.  Power and dynamic noise considerations in high-performance CMOS VLSI , 1999 .

[4]  Chandramouli Visweswariah,et al.  Optimization techniques for high-performance digital circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[5]  Anantha P. Chandrakasan,et al.  Design of portable systems , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[6]  L. Gal,et al.  On-chip cross talk-the new signal integrity challenge , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[7]  D. Auvergne,et al.  A comprehensive delay macro modeling for submicrometer CMOS logics , 1999, IEEE J. Solid State Circuits.

[8]  Qi-Jun Zhang,et al.  Signal integrity optimization of high-speed VLSI packages and interconnects , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).