Development of Embedded Redistribution Layer-Based Silicon Interposer for 3-D Integration

Silicon interposers that are typically composed of redistribution layers (RDLs) and through-silicon vias have become a popular alternative approach to achieve 3-D integration. However, issues including the long metallization duration and the risk of unacceptable interfacial resistance or even disconnection are prohibiting their wider adoption. In this paper, by substituting RDLs with conductive polymer-filled trenches at the bonding interface, a silicon interposer architecture with faster fabrication speed and better interfacial connection was developed. Ag-based and carbon-based (C-based) conductive polymers with different viscosities were tested under varying vacuum suction conditions. It was found that the filling ratio would increase more efficiently with the driving pressure. Besides, measurements indicated the average resistance of channels filled with Ag-based conductive polymers was in the range of 40– $55~\Omega $ . Furthermore, their resistivity stability and bonding strength to Cu and Al had proven to be promising during the temperature increase.

[1]  A. Etcheberry,et al.  Bottom-up filling optimization for efficient TSV metallization , 2010 .

[2]  Micha Tomkiewicz,et al.  Environmental Aspects of Electrodeposition , 2011 .

[3]  M. Bakir,et al.  3D integration of CMOS and MEMS using mechanically flexible interconnects (MFI) and through silicon vias (TSV) , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[4]  El Gowini.  Overcoming Some of the Challenges in 3D Micro-Assembly Techniques to Package MEMS Devices , 2014 .

[5]  Eric Beyne.  Through-Silicon via Technology for 3D IC , 2011 .

[6]  G. Stemme,et al.  Very high aspect ratio through silicon vias (TSVs) using wire bonding , 2013, 2013 Transducers & Eurosensors XXVII: The 17th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS & EUROSENSORS XXVII).

[7]  Matti Mantysalo,et al.  Inkjet filling of TSVs with silver nanoparticle ink , 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

[8]  Shinpei Ogawa,et al.  RF-MEMS switch with through-silicon via by the molten solder ejection method , 2012 .

[9]  R. Beica,et al.  Advanced Metallization for 3D Integration , 2008, 2008 10th Electronics Packaging Technology Conference.

[10]  M. Dickey,et al.  Ultrastretchable Fibers with Metallic Conductivity Using a Liquid Metal Alloy Core , 2013 .

[11]  Xiaolin Zhao,et al.  Design, simulation and fabrication of a flexible bond pad with a hollow annular protuberance to improve the thermal fatigue lifetime for through-silicon vias , 2014 .

[12]  V. Fiori,et al.  Numerical Analysis of the Reliability of Cu/low-k Bond Pad Interconnections Under Wire Pull Test: Application of a 3D Energy Based Failure Criterion , 2007, 2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007.

[13]  T. Anthopoulos,et al.  High‐Performance Polymer‐Small Molecule Blend Organic Transistors , 2009 .

[14]  Jung-Lok Yu,et al.  Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package , 2009 .

[15]  L. Leung,et al.  Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates , 2005, IEEE Transactions on Microwave Theory and Techniques.

[16]  Jin-Hu Dou,et al.  A BDOPV‐Based Donor–Acceptor Polymer for High‐Performance n‐Type and Oxygen‐Doped Ambipolar Field‐Effect Transistors , 2013, Advanced materials.

[17]  H. Y. Li,et al.  Fast electroplating TSV process development for the via-last approach , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[18]  M. Kim,et al.  Cu Bottom-Up Filling for Through Silicon Vias with Growing Surface Established by the Modulation of Leveler and Suppressor , 2013 .

[19]  T. Moffat,et al.  Extreme Bottom-Up Superfilling of Through-Silicon-Vias by Damascene Processing: Suppressor Disruption, Positive Feedback and Turing Patterns , 2012 .

[20]  I. Shubin,et al.  Package demonstration of an interposer with integrated TSVs and flexible compliant interconnects , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[21]  Jong Hyeong Kim,et al.  Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking , 2011, Microelectron. Reliab..

[22]  P. Chausse,et al.  Through Silicon Via polymer filling for 3D-WLP applications , 2010, 3rd Electronics System Integration Technology Conference ESTC.

[23]  Chang-Woo Lee,et al.  Advanced TSV filling method with Sn alloy and its reliability , 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

[24]  H. Reichl,et al.  High aspect ratio TSV copper filling with different seed layers , 2008, 2008 58th Electronic Components and Technology Conference.

[25]  E. Beyne,et al.  Reliability concerns in copper TSV's: Methods and results , 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.