Exploiting loop behavior for data cache leakage reduction
暂无分享,去创建一个
[1] K. Asanović,et al. Dynamic fine-grain leakage reduction using leakage-biased bitlines , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.
[2] Wei Zhang,et al. A compiler approach for reducing data cache energy , 2003, ICS '03.
[3] Gurindar S. Sohi,et al. A static power model for architects , 2000, MICRO 33.
[4] Luca Benini,et al. System-level power optimization: techniques and tools , 2000, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).
[5] M. Kandemir,et al. Exploiting program hotspots and code sequentiality for instruction cache leakage management , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..
[6] Wei Zhang,et al. Compiler-directed instruction cache leakage optimization , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..
[7] William J. Bowhill,et al. Design of High-Performance Microprocessor Circuits , 2001 .
[8] Kaushik Roy,et al. Reducing leakage in a high-performance deep-submicron instruction cache , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[9] Steven S. Muchnick,et al. Advanced Compiler Design and Implementation , 1997 .
[10] M. Martonosi,et al. Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, Proceedings 28th Annual International Symposium on Computer Architecture.
[11] Trevor Mudge,et al. Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..