Routing for array-type FPGA's
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[1] Malgorzata Marek-Sadowska,et al. Time-multiplexed routing resources for FPGA design , 1996 .
[2] Douglas Chang,et al. On The Np-completeness Of Regular 2-d Fpga Routing Architectures And A Novel Solution , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[3] Akihiro Hashimoto,et al. Wire routing by optimizing channel assignment within large apertures , 1971, DAC.
[4] Malgorzata Marek-Sadowska,et al. Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing , 1995, 32nd Design Automation Conference.
[5] C. Liu,et al. Routing for Symmetric FPGA's and FPIC's , 1997 .
[6] Malgorzata Marek-Sadowska,et al. Graph based analysis of 2-D FPGA routing , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Jeffrey D. Ullman,et al. Worst-Case Performance Bounds for Simple One-Dimensional Packing Algorithms , 1974, SIAM J. Comput..
[8] Allen C.-H. Wu,et al. A performance and routability-driven router for FPGAs considering path delays , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Yao-Wen Chang,et al. A New Global Routing Algorithm For FPGAs , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[10] Harry Hsieh,et al. A user programmable reconfigurable logic array , 1986 .
[11] Mikael Palczewski. Plane parallel A* maze router and its application to FPGAs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[12] Malgorzata Marek-Sadowska,et al. Graph based analysis of FPGA routing , 1993, EURO-DAC.
[13] I. Williams. Programmable logic arrays for prototype computer implementation , 1990 .
[14] C. L. Liu,et al. Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture , 1994, 31st Design Automation Conference.
[15] Yao-Wen Chang,et al. A new global routing algorithm for FPGAs , 1994, ICCAD '94.
[16] Allen C.-H. Wu,et al. A Performance and Routability Driven Router for FPGAs Considering Path Delays , 1995, 32nd Design Automation Conference.
[17] Shih-Chieh Chang,et al. Layout Driven Logic Synthesis for FPGAs , 1994, 31st Design Automation Conference.
[18] Malgorzata Marek-Sadowska,et al. On computational complexity of a detailed routing problem in two dimensional FPGAs , 1994, Proceedings of 4th Great Lakes Symposium on VLSI.
[19] Malgorzata Marek-Sadowska,et al. An efficient router for 2-D field programmable gate array , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[20] William S. Carter,et al. Third-generation architecture boosts speed and density of field-programmable gate arrays , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.
[21] Gabriel Robins,et al. New performance-driven FPGA routing algorithms , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[22] Jonathan Rose. LocusRoute: a parallel global router for standard cells , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[23] A. El Gamal,et al. Architecture of field-programmable gate arrays , 1993, Proc. IEEE.
[24] Jonathan Rose,et al. A detailed router for field-programmable gate arrays , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..