Effect Of Plastic Deformation Of Silicon Wafers On Overlay

Direct measurement of lateral distortion in (100) silicon wafers reveals random shifts as large as 0.5 μm resulting from high-temperature processes commonly used during the manufacture of integrated circuits. Such shifts are commensurate in size with the dimensional tolerances required for high-performance integrated circuits, and therefore pose a serious problem in the manufacture of devices requiring submicrometer lines or overlay accuracy of less than 1 μm. The effect has been studied after processing in various conditions; the lateral or in-plane distortions appear to increase as wafers undergo multiple-processing steps.