Specification , Verification and Synthesis : An Example

In this article we present various approaches to specifying and verifying a simple system. The first approach is to specify the system in a state based language and express the requirements in an appropriate temporal logic. Within state based languages three approaches to specifying behaviour are explored. The first approach is to use traditional imperative techniques, the second is to use a declarative style for explicit transitions and third is to use synthesis ideas given a general transition system and certain logical requirements. The second major approach is based on programming with an imperative but synchronous language. The paper identifies the advantages of a mixed declarative and state based approach. It also indicates the power of an appropriate synthesis framework to obtain general solutions.