Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions

Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Even in the sub-50 nm region, short-channel effects-V/sub th/ shift and S-factor degradation-are suppressed very well. The impact ionization rate falls significantly as Vd falls below 1.5 V. It is found that, in the case of Vd less than 1.5 V, hot-carrier degradation is not a serious problem even in the sub-50 nm region.<<ETX>>

[1]  R.H. Dennard,et al.  Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's , 1987, IEEE Electron Device Letters.

[2]  A.T. Wu,et al.  Deep-submicrometer MOS device fabrication using a photoresist-ashing technique , 1988, IEEE Electron Device Letters.

[3]  T. Chan,et al.  Performance and hot-carrier reliability of deep-submicrometer CMOS , 1989, International Technical Digest on Electron Devices Meeting.

[4]  Shinji Okazaki,et al.  0.1 mu m CMOS devices using low-impurity-channel transistors (LICT) , 1990, International Technical Digest on Electron Devices.

[5]  M. Dutoit,et al.  Mix and match lithography for 0.1 mm MOSFET fabrication , 1991 .

[6]  T. Yoshitomi,et al.  An SPDD p-MOSFET structure suitable for 0.1 and sub 0.1 micron channel length and its electrical characteristics , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[7]  Jeffrey Bokor,et al.  High performance 0.1- mu m room temperature Si MOSFETs , 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

[8]  H. Iwai,et al.  A New Scaling Methodology For The 0.1 - 0.025/spl mu/m MOSFET , 1993, Symposium 1993 on VLSI Technology.