Minimizing switchings of the function units through binding for low power

This paper considers minimizing the switchings of the function units in high-level synthesis. Switching activities on the function units are gathered through profiling the data-flow graph of the design at hand. Several thousands of random input streams are generated and used for such profiling. A genetic algorithm is employed for creation of a wide variety of random input patterns which are critical to measuring the switching activities. The switching activities are obtained and stored in a matrix. The problem of binding the function units for low power is then formulated and solved by using the proposed method. Based on the simulations, a power saving of 8%-24%, due to reduced switchings, is indicated for the considered standard benchmarks.

[1]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  Niraj K. Jha,et al.  An iterative improvement algorithm for low power data path synthesis , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[3]  Catherine H. Gebotys.  Low energy memory and register allocation using network flow , 1997, DAC.

[4]  Sharad Malik,et al.  Guarded evaluation: pushing power management to logic synthesis/design , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Niraj K. Jha,et al.  An iterative improvement algorithm for low power data path synthesis , 1995, ICCAD.

[6]  José C. Monteiro,et al.  Scheduling techniques to enable power management , 1996, DAC '96.

[7]  Jordi Cortadella,et al.  High-level synthesis techniques for reducing the activity of functional units , 1995, ISLPED '95.

[8]  Massoud Pedram,et al.  Register Allocation and Binding for Low Power , 1995, 32nd Design Automation Conference.