Sub-10 µA data reception with low latency using a 180-nm CMOS wake-up receiver at 868 MHz

This paper shows the benefits of a sub-10 µA wake-up receiver circuit used for wireless data reception with reaction times down to 60 ms. The wake-up receiver is a wireless receiver which continuously scans the radio channel for particular pseudonoise sequences. Having received and decoded the sequence, the wake-up receiver triggers different actions in smart objects. The wake-up receiver offers a scalable current consumption between 2.4 µA and 99 µA and is very suitable for mobile battery-operated smart objects. Details on correlation codes and two proposed protocol schemes for radio channels with bit error rates above 10% are described.

[1]  Xiaoyan Wang,et al.  A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  Anantha Chandrakasan,et al.  A 350μW CMOS MSK transmitter and 400μW OOK super-regenerative receiver for Medical Implant Communications , 2009, 2008 IEEE Symposium on VLSI Circuits.

[3]  S. Gambini,et al.  A 52 $\mu$ W Wake-Up Receiver With $-$ 72 dBm Sensitivity Using an Uncertain-IF Architecture , 2009, IEEE Journal of Solid-State Circuits.

[4]  Kofi A. A. Makinwa,et al.  A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).