120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit

A new device structure named IDLDMOS is proposed to overcome the power LDMOS limit (R/sub on, sp/ /spl prop/ BV/sub dss//sup 2.5/). The concept is based on replacing LDMOS lightly doped n-drift region by moderately doped alternating p and n layers of suitable dimension and doping. Off state requirement is achieved by mutual lateral-depletion of the alternating layers. Using small identical lateral width for both p and n layers, a doping concentration of up to two orders of magnitude higher than n-drift concentration in a conventional case can he achieved to reduce the on-resistance R/sub on/. The simulated 120 V IDLDMOS on SOI substrate has shown a R/sub on/ value that is about 38% of the corresponding R/sub on/ value of a conventional n/sup -/ LDD type LDMOS. At a R/sub on, sp/ value of 1.15 m/spl Omega/-cm/sup 2/ with BV/sub dss/ of 124 V, IDLDMOS has exceeded the conventional LDMOS limit. Compared to conventional LDMOS, IDLDMOS is less prone to quasisaturation at high gate and drain voltage due to its higher drain doping. Isothermal simulation has shown that there was no deterioration in both AC and transient performance between the two devices. Nevertheless, the lower V/sub d, sat/ of LDLDMOS is expected to yield a higher g/sub m/ at the same level of current conduction as in the conventional structure.

[1]  C.A.T. Salama,et al.  Integration of high-voltage NMOS devices into a sub micron BiCMOS process using simple structural changes , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[2]  C. Tsai,et al.  16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technology , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[3]  V. Parthasarathy,et al.  A 33 V, 0.25 m/spl Omega/-cm/sup 2/ n-channel LDMOS in a 0.65 /spl mu/m smart power technology for 20-30 V applications , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[4]  Taylor R. Efland,et al.  A performance comparison between new reduced surface drain "RSD" LDMOS and RESURF and conventional planar power devices rated at 20 V , 1997, Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's.

[5]  J. Tihanyi,et al.  A new generation of high voltage MOSFETs breaks the limit line of silicon , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[6]  Chenming Hu,et al.  Optimum doping profile for minimum ohmic resistance and high-breakdown voltage , 1979 .

[7]  L. Vestling,et al.  A novel high-frequency high-voltage LDMOS transistor using an extended gate RESURF technology , 1997, Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's.

[8]  F. Fang,et al.  Hot Electron Effects and Saturation Velocities in Silicon Inversion Layers , 1970 .

[9]  J. Olsson,et al.  Integration of a novel high-voltage Giga-Hertz DMOS transistor into a standard CMOS process , 1995, Proceedings of International Electron Devices Meeting.

[10]  T. Fujihira,et al.  Simulated superior performances of semiconductor superjunction devices , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).