Fixed-bit-width multiplier with high accuracy and low energy consumption properties

The present invention relates to the technical field of integrated circuits, and in particular to a fixed-bit-width multiplier with high accuracy and low energy consumption properties. The fixed-bit-width multiplier with the high accuracy and low energy consumption properties comprises a CSD encode circuit, a high position partial product generation circuit, a low position compensation circuit and a partial product compression circuit, wherein an input port of the CSD encode circuit is connected to external input data, and an output port of the CSD encode circuit is connected to the high position partial product generation circuit and the low position compensation circuit; the high position partial product generation circuit is connected to the external input data, and an output port of the high position partial product generation circuit is connected to the partial product compression circuit; the low position compensation circuit is connected to the external input data, and an output port of the low position compensation circuit is connected to the partial product compression circuit; and an output port of the partial product compression circuit is connected to the external input data. The present invention has the beneficial effects that a fixed-bit-width multiplier with low energy consumption and a relatively high speed, and a practical fixed-bit-width multiplier design with high accuracy and low energy consumption are achieved. The fixed-bit-width multiplier of the present invention is particularly suitable for implementation of a high-accuracy multiplication with low energy consumption and a fixed bit width.