CMOS 40 GHz divide-by-5 injection-locked frequency divider
暂无分享,去创建一个
A 40 GHz divide-by-5 injection-locked frequency divider fabricated in a CMOS 0.18 μm process is presented. By utilising a series-LC bandpass filter that is connected to the common-mode node of the differential injection pair to bypass the unwanted second harmonic and produce high impedance for the desired fourth-order harmonic, the fourth-order harmonic (4 f 0 ) is peaked and mixed with input signals (at 5 f 0 ) to achieve the output frequency f 0 (=5 f 0 - 4 f 0 ). With an injection power of -3 dBm, the measured maximum locking range is 735 MHz at a tuning voltage of 0.8 V. The total locking range covers 39.36-42.1 GHz as the tuning voltage rises from 0 to 1.8 V. This divider consumes 18 mW at 1 V supply voltage.
[1] Liang-Hung Lu,et al. A harmonic injection-locked frequency divider in 0.18-/spl mu/m SiGe BiCMOS , 2006, IEEE Microwave and Wireless Components Letters.
[2] Tang-Nian Luo,et al. 77 GHz CMOS injection-locked Miller frequency divider , 2009 .
[3] Jri Lee,et al. A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology , 2008, IEEE Journal of Solid-State Circuits.
[4] Huei Wang,et al. A 50 GHz Divide-by-4 Injection Lock Frequency Divider Using Matching Method , 2008, IEEE Microwave and Wireless Components Letters.