It is a known fact that 90% of the execution time of high performance applications are spent in nested loop programs which offer a tremendous potential of acceleration due to inherent parallelism. Furthermore, streaming applicatio ns consisting of multiple communicating loops from fields of signa l processing, medical imaging, financial computing require h gh performance computing. The FPGAs offer huge amounts of resources for realization of massively parallel hardware a ccelerators. The major goal of the PARO tool developed at the University of Erlangen-Nuremberg is automatic generation of (a)hardware accelerators for FPGAs from algorithms (especially nested loops) descriptions [3], (b) accelerator pip eline, and (c) interface circuits and drivers for system integrati on. The methodology is based on the intuitive and efficient paral lelization in the polytope model [2]. There exists only a few tools for hardware generation like PICO from Synfora that are also based on the polytope model. The design trajectory of PARO is shown in Fig. 1. The novelty of the tool design flow is summarized as follows:
[1]
Paul Feautrier,et al.
Automatic Parallelization in the Polytope Model
,
1996,
The Data Parallel Programming Model.
[2]
Jürgen Teich,et al.
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
,
2006,
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).
[3]
Steven S. Muchnick,et al.
Advanced Compiler Design and Implementation
,
1997
.
[4]
Jürgen Teich,et al.
Resource constrained and speculative scheduling of an algorithm class with run-time dependent conditionals
,
2004
.
[5]
Jürgen Teich,et al.
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
,
2008,
ARC.