论文信息 - Patterning sub-30-nm MOSFET gate with i-line lithography

Patterning sub-30-nm MOSFET gate with i-line lithography

We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gates. These techniques require neither specific equipment nor materials. These can be used to fabricate experimental devices with line width beyond the limit of optical lithography or high-throughput e-beam lithography. They provide 25-nm gate patterns with i-line lithography and sub-30-nm pattern with e-beam lithography. A 40-nm gate channel length nMOSFET is demonstrated.

[1] Chenming Hu,et al. Ultra-thin body SOI MOSFET for deep-sub-tenth micron era , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[2] A.T. Wu,et al. Deep-submicrometer MOS device fabrication using a photoresist-ashing technique , 1988, IEEE Electron Device Letters.

[3] T. Matsuno,et al. 0.1 μm AlGaAs/InGaAs high electron mobility transistor fabrication by the new method of thinned resist pattern reversed by metal , 1996 .

[4] Hiroshi Iwai,et al. Fabrication of sub‐50‐nm gate length n‐metal–oxide–semiconductor field effect transistors and their electrical characteristics , 1995 .

[5] D. Jeon,et al. Gate technology for 0.1‐μm Si complementary metal–oxide–semiconductor using g‐line exposure and deep ultraviolet hardening , 1994 .