Crosstalk aware transient error correction coding technique for NoC links

Abstract In Deep Sub Micron (DSM) technology, the critical issues in the NoC interconnect design are to meet the performance, power consumption requirements of the SoC and to address reliability simultaneously, interconnect delay, power consumption and crosstalk noise. It is essential to select an optimal coding technique to improve communication reliability and reduce self and coupling switching activities. In this paper, Crosstalk Aware Transient Error Correction (CATEC) coding technique is proposed to handle the reliability issues and flit dependent switching activities. The achievable reliability and reduction of switching activities are evaluated using real-time traffics. It is proved that the CATEC technique corrects all the error patterns with one or two transient error bits and few error patterns with six to nine transient error bits. Furthermore, 99% of the error patterns with three, four and five transient error bits are too corrected for a 32 bit flit. This technique considerably reduces flit dependent self and coupling transitions. This results in low power NoC link and even avoids crosstalk to a greater extent.

[1]  Naresh R. Shanbhag,et al.  Area and energy-efficient crosstalk avoidance codes for on-chip buses , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[2]  Cecilia Metra,et al.  Coding scheme for low energy consumption fault-tolerant bus , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[3]  Cecilia Metra,et al.  Exploiting ECC redundancy to minimize crosstalk impact , 2005, IEEE Design & Test of Computers.

[4]  Xinan Zhou,et al.  Performance evaluation of network-on-chip interconnect architectures , 2009 .

[5]  Igor L. Markov,et al.  Error-correction and crosstalk avoidance in DSM busses , 2004, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Chih-Peng Fan,et al.  Novel low-power bus invert coding methods with crosstalk detector , 2011 .

[7]  K. Paramasivam,et al.  Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip , 2012 .

[8]  K. Somasundaram,et al.  Design and evaluation of virtual channel router for mesh-of-grid based NoC , 2014, 2014 International Conference on Electronics and Communication Systems (ICECS).

[9]  Zhonghai Lu,et al.  Multi-bit transient fault control for NoC links using 2D fault coding method , 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[10]  Yehea I. Ismail,et al.  Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  G. Seetharaman,et al.  Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link , 2014, J. Electron. Test..

[12]  T. K. Ramesh,et al.  Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC , 2020, IEEE Access.

[13]  Tomás Lang,et al.  Working-zone encoding for reducing the energy in microprocessor address buses , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Makoto Ikeda,et al.  Low power chip interface based on bus data encoding with adaptive code-book method , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[15]  Eby G. Friedman,et al.  Effect of shield insertion on reducing crosstalk noise between coupled interconnects , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[16]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[17]  Paul Ampadu,et al.  Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[18]  Z. Shirmohammadi,et al.  S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCs , 2015, 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

[19]  Chunjie Duan,et al.  Efficient On-Chip Crosstalk Avoidance CODEC Design , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Ahmad Khademzadeh,et al.  Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Partha Pratim Pande,et al.  Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  K. Somasundaram,et al.  Design and Evaluation of 3D NoC Routers with Quality-of-Service (QoS) Mechanism for Multi-core Systems , 2016 .

[23]  Somasundaram Kanagasabapathi,et al.  A Routing Algorithm and a Router Architecture for 3D NoC , 2019, Comput. Sci..

[24]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[25]  Kevin Skadron,et al.  Odd/even bus invert with two-phase transfer for buses with coupling , 2002, ISLPED '02.

[26]  Yehea I. Ismail,et al.  Reducing the data switching activity on serial link buses , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[27]  G. Seetharaman,et al.  Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link , 2014, Int. J. Comput. Appl. Technol..

[28]  Naresh R. Shanbhag,et al.  Coding for low-power address and data busses: a source-coding framework and applications , 1998, Proceedings Eleventh International Conference on VLSI Design.

[29]  G. Seetharaman,et al.  Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links , 2013, Microprocess. Microsystems.

[30]  N. S. Murty,et al.  Hamming Based Multiple Transient Error Correction Code for NoC Interconnect , 2020 .

[31]  Luca Benini,et al.  Error control schemes for on-chip communication links: the energy-reliability tradeoff , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Tughrul Arslan,et al.  Low power system on chip bus encoding scheme with crosstalk noise reduction capability , 2006 .

[33]  Bo Fu,et al.  On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[34]  Vincenzo Catania,et al.  Data Encoding Schemes in Networks on Chip , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[35]  Mohamed Chouikha,et al.  Joint Crosstalk Aware Burst Error Fault Tolerance Mechanism for Reliable on-Chip Communication , 2020, IEEE Transactions on Emerging Topics in Computing.

[36]  Partha Pratim Pande,et al.  Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[37]  Mansour Shafaei,et al.  FiRot: An Efficient Crosstalk Mitigation Method for Network-on-Chips , 2010, 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing.

[38]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.