Altitude SEE Test European Platform (ASTEP): Project Overview, First Results in CMOS 130nm and Perspectives

The "Altitude SEE Test European Platform" (ASTEP) is dedicated to real-time soft-error rate ( SER) testing of semiconductor memories. The platform, located in the French Alps on the "Plateau de Bure" at 2552m, has been operational since March 2006. This test facility includes a pro prietary automatic test equipment specially designed for sta tic memory (SRAM) testing and secured remote control operation via internet. First real-life SER measurements on 3.6 Gbit of SRAMs manufactured in CMOS 130 nm technology are reported, as well as the comparison between real-life and accelerated SER. Project perspectives for CMOS 65nm SRAMs are finally reported.