New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder

This paper proposes a new degree computationless modified Euclid (DCME) algorithm and its dedicated architecture for Reed-Solomon (RS) decoder. This architecture has low hardware complexity compared with conventional modified Euclid (ME) architectures, since it can completely remove the degree computation and comparison circuits. The architecture employing a systolic array requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t+2 basic cells has regularity and scalability since it uses only one processing element. Hence, the proposed DCME architecture provides the short latency and low-cost RS decoding. The DCME architecture has been synthesized using the 0.25-mum Faraday CMOS standard cell library and operates at 200 MHz. The gate count of the DCME architecture is 21 760. Hence, the RS decoder using the proposed DCME architecture can reduce the total gate count by at least 23% and the total latency to at least 10% compared with conventional ME decoders

[1]  Marco Platzner,et al.  Online scheduling for block-partitioned reconfigurable devices , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[3]  Chih-Tsun Huang,et al.  VLSI design of a high speed pipelined Reed-Solomon CODEC , 1996 .

[4]  Framing structure , channel coding and modulation for digital terrestrial television , 2022 .

[5]  Rudy Lauwereins,et al.  Designing an operating system for a heterogeneous reconfigurable SoC , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[6]  Kui Liu,et al.  Algorithm-based low-power/high-speed Reed-Solomon decoder design , 2000 .

[7]  Trieu-Kien Truong,et al.  On decoding of both errors and erasures of a Reed-Solomon code using an inverse-free Berlekamp-Massey algorithm , 1999, IEEE Trans. Commun..

[8]  Xia Fang,et al.  A new VLSI design for decoding of Reed-Solomon codes based on ASIP [HDTV] , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[9]  T. K. Matsushima,et al.  Parallel architecture for high-speed Reed-Solomon codec , 1998, ITS'98 Proceedings. SBT/IEEE International Telecommunications Symposium (Cat. No.98EX202).

[10]  Eung-Bae Kim,et al.  Architecture for decoding adaptive Reed-Solomon codes with variable block length , 2002, IEEE Trans. Consumer Electron..

[11]  Paolo Ienne,et al.  Virtual memory window for a portable reconfigurable cryptography coprocessor , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[12]  A. Abou-El-Azm,et al.  Error rates for non-coherent demodulation FCMA with Reed-Solomon codes in fading satellite channel , 1999, 1999 IEEE 49th Vehicular Technology Conference (Cat. No.99CH36363).

[13]  Hanho Lee.  Modified Euclidean algorithm block for high-speed Reed-Solomon decoder , 2001 .

[14]  J. H. Yuen,et al.  A VLSI design of a pipeline Reed-Solomon decoder , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[15]  Allen H. Levesque,et al.  Error-control techniques for digital communication , 1985 .

[16]  Myung Hoon Sunwoo,et al.  Design of a high-speed Reed-Solomon decoder , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[17]  Leilei Song,et al.  VLSI design of Reed-Solomon decoder architectures , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[18]  Ye Yi-zheng,et al.  Design and implementation of high-speed Reed-Solomon decoder , 2002, ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605).

[19]  Monk-Ping Leong,et al.  Pilchard - A Reconfigurable Computing Platform with Memory Slot Interface , 2001, IEEE Symposium on Field-Programmable Custom Computing Machines.

[20]  Stephen B. Wicker,et al.  Reed-Solomon Codes and Their Applications , 1999 .