VLSI Floating Resistors for Neural Type Cell Arrays

Two novel CMOS circuit designs implementing floating resistors are introduced, using the structure of a two-transistor CMOS bilateral linear resistor in the first configuration and two two-transistor CMOS bilateral linear resistors and cascode current mirrors in the second configuration. Linearity is achieved through nonlinearity cancellation via current mirrors over an applied range of ±5V. PSpice simulation results using parameters of MOSIS transistors are presented to verify the theory. These floating resistors can be used for coupling weights in VLSI neural-type cell arrays.