A design method of CPR for wide voltage design

[1]  Yoshihiro Hayashi,et al.  A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines , 2012, IEEE Journal of Solid-State Circuits.

[2]  Tao-Tao Zhu,et al.  SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor , 2017, IEICE Electron. Express.

[3]  David Blaauw,et al.  The limit of dynamic voltage scaling and insomniac dynamic voltage scaling , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Massimo Alioto.  Ultra-low power design approaches for IoT , 2014, 2014 IEEE Hot Chips 26 Symposium (HCS).

[5]  Luciano Lavagno,et al.  De-synchronization: asynchronous circuits from synchronous specifications , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[6]  Ahmad Kharaz,et al.  An efficient adaptive voltage scaling using delay monitor unit , 2015, 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

[7]  Mingoo Seok,et al.  Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique , 2015, IEEE Journal of Solid-State Circuits.

[8]  Satyam Dwivedi,et al.  Adaptative Techniques to Reduce Power in Digital Circuits , 2011 .

[9]  Peter A. Beerel,et al.  Ultra-low power pass-transistor-logic-based delay line design for sub-threshold applications , 2016 .

[10]  Kaushik Roy,et al.  CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Keith A. Bowman.  Adaptive and Resilient Circuits: A Tutorial on Improving Processor Performance, Energy Efficiency, and Yield via Dynamic Variation , 2018, IEEE Solid-State Circuits Magazine.

[12]  P.J. Restle,et al.  Timing uncertainty measurements on the Power5 microprocessor , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[13]  Youhua Shi,et al.  Timing monitoring paths selection for wide voltage IC , 2016, IEICE Electron. Express.

[14]  J. Tschanz,et al.  Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance , 2009, 2009 Symposium on VLSI Circuits.

[15]  Kenneth S. Stevens,et al.  Path Based Timing Validation for Timed Asynchronous Design , 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

[16]  Doris Schmitt-Landsiedel,et al.  The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits , 1996, ISLPED '96.

[17]  Peter A. Beerel,et al.  Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications , 2016, 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

[18]  Stephan Henzler,et al.  In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations , 2007, IEEE Journal of Solid-State Circuits.

[19]  Paolo A. Aseron,et al.  A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance , 2011, IEEE Journal of Solid-State Circuits.

[20]  Manoj Sachdev,et al.  Variation-Aware Adaptive Voltage Scaling System , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Cecilia Metra,et al.  On-line detection of logic errors due to crosstalk, delay, and transient faults , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[22]  Shen-Iuan Liu,et al.  A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS , 2016, IEEE J. Solid State Circuits.

[23]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[24]  Jian Liu,et al.  Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages , 2013, 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems.

[25]  Georg Georgakos,et al.  Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling , 2012 .