The integrated implementation of Whirlpool and AES on FPGA

Advanced Encryption Standard (AES) is one of the latest symmetric key cryptosystem standard, which is proposed to replace DES. Whirlpool is a famous hash encryption algorithm that processes the building blocks in a similar way. Although some slight differences are presented, implementing an integrated design of AES and Whirlpool on the FPGA can reduce the overall area. Further more, it provides a scaleable implementation of trust platform module (TPM) which is the trust root of trusted computing. In this paper, an optimized design of the register array is addressed, and it reduces about 65% of the area and makes this integrated design be implemented in low-end FPGAs.

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