Design of a Algorithmic ADC for Digital PFC Controller

A 11b 100KS/s Algorithmic ADC for Digital PFC controller is proposed. The proposed Algorithmic ADC structure for 11bit resolution is based on a cyclic architecture to reduce chip area and power consumption. The prototype Algorithmic ADC implemented with a 0.18um 1Poly-3Metal CMOS process shows a SNDR 66.7dB and ENOB 10.78bits. And the current consumption is about 780uA at 100KS/s and 5V. The occupied active die area is .

[2]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[3]  P.J. Hurst,et al.  A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[4]  R. Castello,et al.  A ratio-independent algorithmic analog-to-digital conversion technique , 1984, IEEE Journal of Solid-State Circuits.

[5]  P.G.A. Jespers,et al.  A CMOS 13-b cyclic RSD A/D converter , 1992, IEEE Journal of Solid-State Circuits.

[6]  G. Nicollini,et al.  A 2.7V 350/spl mu/W 11-b algorithmic analogue-to-digital converter with single-ended multiplexed inputs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[8]  Cheng-Chung Shih,et al.  Ratio independent cyclic A/D and D/A conversion using a recirculating reference approach , 1983 .

[9]  Ying-Yu Tzou,et al.  Load adaptive control for mixed-signal PFC control IC , 2009, 2009 International Conference on Power Electronics and Drive Systems (PEDS).