A Process-Oriented Streaming System Design Paradigm for FPGAs

This paper presents a streaming system design paradigm that allows developers to model streaming applications and their FPGA-based many-core hardware architectures as processes and channels. We have developed a programming language called System-Oberon, together with a run-time library, a hardware library implemented on an FPGA, and a compiler to automate the system design flow. In general, the proposed paradigm represents a software-driven approach to the streaming system designs on FPGAs. Compared to the existing solutions, our system design paradigm and its tool chain allow the automatic construction of a completely autonomous system on an FPGA, support the task-level parallelism from both software and hardware levels, and avoid the need for hardware programming work for application developers. These features make the proposed approach advantageous in achieving better results regarding the system’s performance, power consumption, design reuse and time-to-market. To prove the applicability of our approach, a monitor for real-time ECG signal analysis was built and analyzed for its performance, size, power consumption and development time.

[1]  Willis J. Tompkins,et al.  A Real-Time QRS Detection Algorithm , 1985, IEEE Transactions on Biomedical Engineering.

[2]  John Wawrzynek,et al.  Stream Computations Organized for Reconfigurable Execution (SCORE) , 2000, FPL.

[3]  Lisa Ling Liu A DDR2 SDRAM interface for Xilinx ML505 evaluation platform , 2009 .

[4]  Niklaus Wirth,et al.  The oberon system , 1989, Softw. Pract. Exp..

[5]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[6]  P. Hamilton,et al.  Open source ECG analysis , 2002, Computers in Cardiology.

[7]  Alexandru Turjan,et al.  System design using Khan process networks: the Compaan/Laura approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[8]  Maya Gokhale,et al.  Stream-oriented FPGA computing in the Streams-C high level language , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[9]  Mickaël Raulet,et al.  OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems , 2008, CARN.

[10]  Ling Liu A 12-core processor implementation on FPGA , 2009 .

[11]  Dominique Lavenier,et al.  Evaluation of the streams-C C-to-FPGA compiler: an applications perspective , 2001, FPGA '01.

[12]  Erwin A. de Kock,et al.  YAPI: application modeling for signal processing systems , 2000, Proceedings 37th Design Automation Conference.

[13]  Henry Hoffmann,et al.  A stream compiler for communication-exposed architectures , 2002, ASPLOS X.

[14]  P Caminal,et al.  Automatic detection of wave boundaries in multilead ECG signals: validation with the CSE database. , 1994, Computers and biomedical research, an international journal.