Fault-aware routing approach for mesh-based Network-on-Chip architecture

[1]  M. G. Harbour,et al.  Response-time analysis of mesh-based many-core systems , 2022, J. Syst. Archit..

[2]  Ankur Gogoi,et al.  Application-Driven Fault Identification in NoC Designs , 2021, VLSI and Hardware Implementations Using Modern Machine Learning Methods.

[3]  Masaru Fukushi,et al.  A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage of Faulty Nodes, Not Always Detour , 2020 .

[4]  Jean-Philippe Diguet,et al.  ECTM: A network-on-chip communication model to combine task and message schedulability analysis , 2020, J. Syst. Archit..

[5]  P. Veda Bhanu,et al.  Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning , 2020, 2020 24th International Symposium on VLSI Design and Test (VDAT).

[6]  Ahmed Louri,et al.  CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning , 2020, IEEE Transactions on Parallel and Distributed Systems.

[7]  Ahmed Louri,et al.  High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Linga Reddy Cenkeramaddi,et al.  Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement , 2018, 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

[9]  John Jose,et al.  Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip , 2018, VDAT.

[10]  Santanu Chattopadhyay,et al.  Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design , 2018, IEEE Transactions on Computers.

[11]  Magdy A. Bayoumi,et al.  Self-healing router architecture for reliable network-on-chips , 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[12]  John Jose,et al.  Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips , 2017, IET Comput. Digit. Tech..

[13]  Indranil Sengupta,et al.  Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs , 2017, Integr..

[14]  Lu Wang,et al.  A runtime fault-tolerant routing algorithm based on region flooding in NoCs , 2016, Microprocess. Microsystems.

[15]  Farshad Safaei,et al.  An efficient fault-tolerant routing algorithm in NoCs to tolerate permanent faults , 2016, The Journal of Supercomputing.

[16]  Masoud Daneshtalab,et al.  Fault-tolerant 3-D network-on-chip design using dynamic link sharing , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[17]  Monica Magalhães Pereira,et al.  Enabling NoC Performance Improvement Using a Fault Tolerance Mechanism , 2015, 2015 Brazilian Symposium on Computing Systems Engineering (SBESC).

[18]  Valeria Bertacco,et al.  Highly Fault-tolerant NoC Routing with Application-aware Congestion Management , 2015, NOCS.

[19]  Salvatore Monteleone,et al.  Noxim: An open, extensible and cycle-accurate network on chip simulator , 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[20]  Xiaohang Wang,et al.  Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip , 2014, VLSI-SoC.

[21]  John Jose,et al.  A Novel Energy Efficient Source Routing for Mesh NoCs , 2014, 2014 Fourth International Conference on Advances in Computing and Communications.

[22]  Santanu Chattopadhyay,et al.  A spare link based reliable Network-on-Chip design , 2014, 18th International Symposium on VLSI Design and Test.

[23]  Santanu Chattopadhyay,et al.  A spare router based reliable Network-on-Chip design , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[24]  Radu Marculescu,et al.  A comprehensive and accurate latency model for Network-on-Chip performance analysis , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[25]  Leibo Liu,et al.  A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration , 2013, J. Syst. Archit..

[26]  Axel Jantsch,et al.  Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[27]  Sander Stuijk,et al.  A Case Study into Predictable and Composable MPSoC Reconfiguration , 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

[28]  Hannu Tenhunen,et al.  Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[29]  Dara Rahmati,et al.  Power-efficient deterministic and adaptive routing in torus networks-on-chip , 2012, Microprocess. Microsystems.

[30]  Anantha Chandrakasan,et al.  Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI , 2012, DAC Design Automation Conference 2012.

[31]  Ching-Te Chiu,et al.  On the design and analysis of fault tolerant NoC architecture using spare routers , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[32]  Axel Jantsch,et al.  A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip , 2010, NoCArc '10.

[33]  Camel Tanougast,et al.  A new deadlock-free fault-tolerant routing algorithm for NoC interconnections , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[34]  Ligang Hou,et al.  Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3X3 Mesh Topology Network-on-Chip , 2009, 2009 WRI Global Congress on Intelligent Systems.

[35]  An-Yeu Wu,et al.  Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks , 2008, IEEE Transactions on Computers.

[36]  Amir Hosseini,et al.  A fault-aware dynamic routing algorithm for on-chip networks , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[37]  José González,et al.  Understanding the Thermal Implications of Multi-Core Architectures , 2007, IEEE Transactions on Parallel and Distributed Systems.

[38]  Lorena Anghel,et al.  Essential Fault-Tolerance Metrics for NoC Infrastructures , 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

[39]  Mahmut T. Kandemir,et al.  Fault tolerant algorithms for network-on-chip interconnect , 2004, IEEE Computer Society Annual Symposium on VLSI.

[40]  Jie Wu,et al.  A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model , 2003, IEEE Trans. Computers.

[41]  Kang G. Shin,et al.  Adaptive Fault-Tolerant Deadlock-Free Routing in Meshes and Hypercubes , 1996, IEEE Trans. Computers.

[42]  Suresh Chalasani,et al.  Fault-Tolerant Wormhole Routing Algorithms for Mesh Networks , 1995, IEEE Trans. Computers.

[43]  Marcos Horro,et al.  Simulating the Network Activity of Modern Manycores , 2019, IEEE Access.

[44]  Jürgen Teich,et al.  A Novel NoC-Architecture for Fault Tolerance and Power Saving , 2016 .

[45]  Dominic DiTomaso,et al.  Reactive and Proactive Fault-Tolerant Network-on-Chip Architectures using Machine Learning , 2015 .

[46]  Hossein Pedram,et al.  Investigation of transient fault effects in synchronous and asynchronous Network on Chip router , 2011, J. Syst. Archit..