8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

We report low V<inf>t</inf> (V<inf>t,Lg=1µm</inf>=±0.26V) high performance CMOS devices with ultra-scaled T<inf>inv</inf> down to T<inf>inv</inf>∼8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS T<inf>inv</inf> (2) 220mV lower long channel pMOS V<inf>t</inf> (3) 21%/12% pMOS/nMOS drive current increase at I<inf>off</inf>=100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T<inf>inv</inf> of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.