The first GaAs 10 K-gate sea of gates has been successfully fabricated using junction FETs (JFETs) with a gate length of 0.5 mu m. A basic cell is designed to comprise both a direct coupled FET logic (DCFL) four-NOR circuit and a source coupled FET logic (SCFL) inverter circuit with an identical enhancement-type JFET. Each input and output level is designed to be compatible with Si emitter-coupled-logic (ECL), CMOS, and transistor-transistor-logic (TTL) levels. Unloaded and loaded DCFL gate delays are 21 and 180 ps/gate with power consumption of 0.4 and 0.5 mW/gate, respectively. The toggle frequency of the T-type flip-flop is 3.9 and 4.4 GHz for DCFL and SCFL, respectively. >
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