Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic

In this paper, a new voltage mirror circuit by using carbon nanotubes (CNTs) technology is presented. This circuit is specifically proposed for the application of duplicating multiple-valued and fuzzy dynamic random access memories. The given structure prevents any voltage drop for the capacitor inside the memory cell. As a result, any fanout circuit can be driven. The new structure can be utilised for different multiple-valued logic systems without a change. The unique characteristics of carbon nanotube field effect transistor (CNFET) technology are exploited in this paper to meet the desired design goals. It demonstrates the potentials of CNFET technology in a realistic very large-scale integration application. The proposed design is highly tolerant to D CNT variation and it is also immune to misaligned CNTs. Simulation results demonstrate that it provides sufficient driving capability with reasonable accuracy.

[1]  C. Dekker,et al.  Logic Circuits with Carbon Nanotube Transistors , 2001, Science.

[2]  Keivan Navi,et al.  A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits , 2013, IET Comput. Digit. Tech..

[3]  S. D. Pable,et al.  Performance optimization of CNFET based subthreshold circuits , 2010, 2010 Annual IEEE India Conference (INDICON).

[4]  Sheng Wang,et al.  Carbon nanotube electronics: recent advances , 2014 .

[5]  Arash Ahmadi,et al.  Effect of variability in SWCNT-based logic gates , 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

[6]  H.-S. Philip Wong,et al.  Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[7]  Keivan Navi,et al.  High-Efficient Circuits for Ternary Addition , 2014, VLSI Design.

[8]  K. Maharatna,et al.  Modeling SWCNT Bandgap and Effective Mass Variation Using a Monte Carlo Approach , 2010, IEEE Transactions on Nanotechnology.

[9]  Fabrizio Lombardi,et al.  Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs , 2014, IEEE Transactions on Nanotechnology.

[10]  Soha Hassoun,et al.  Electro-Thermal Analysis of Multi-Fin Devices , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Ken Uchida,et al.  Study on Device Parameters of Carbon Nanotube Field Electron Transistors to Realize Steep Subthreshold Slope of Less than 60 mV/Decade , 2011 .

[12]  Hongjie Dai,et al.  Electrical properties and devices of large-diameter single-walled carbon nanotubes , 2002 .

[13]  Yong-Bin Kim,et al.  CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits , 2011, IEEE Transactions on Nanotechnology.

[14]  H. V. Jayashree,et al.  Ternary SRAM for low power applications , 2012, 2012 International Conference on Communication, Information & Computing Technology (ICCICT).

[15]  Ken Choi,et al.  Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design , 2011, IEEE Transactions on Nanotechnology.

[16]  H. Dai,et al.  Selective Etching of Metallic Carbon Nanotubes by Gas-Phase Reaction , 2006, Science.

[17]  Kenneth L. Shepard,et al.  Hybrid carbon nanotube-silicon complementary metal oxide semiconductor circuits , 2007 .

[18]  Mark S. Lundstrom,et al.  Theory of ballistic nanotransistors , 2003 .

[19]  William A. Goddard,et al.  Energetics, structure, mechanical and vibrational properties of single-walled carbon nanotubes , 1998 .

[20]  Yong-Bin Kim,et al.  A novel design methodology to optimize the speed and power of the CNTFET circuits , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[21]  Jugdutt Singh,et al.  Recent Subthreshold Design Techniques , 2012 .

[22]  Suganth Paul Design and implementation of a sub-threshold wireless BFSK transmitter , 2009 .

[23]  Yong-Bin Kim,et al.  A new SRAM cell design using CNTFETs , 2008, 2008 International SoC Design Conference.

[24]  J. Appenzeller Carbon Nanotubes for High-Performance Electronics V Progress and Prospect The prospect , for nanotube field effect transistors that can compete with silicon technology , .

[25]  Keivan Navi,et al.  Dramatically Low-Transistor-Count High-Speed Ternary Adders , 2013, 2013 IEEE 43rd International Symposium on Multiple-Valued Logic.

[26]  Min-hwa Chi Challenges in Manufacturing FinFET at 20 nm node and beyond , 2012 .

[27]  A. Srivastava,et al.  Numerical Modeling of the I-V Characteristic of Carbon Nanotube Field Effect Transistors (CNT-FETs) , 2008, 2008 40th Southeastern Symposium on System Theory (SSST).

[28]  H.-S. Philip Wong,et al.  Carbon nanotube computer , 2013, Nature.

[29]  Yan Li,et al.  Doping-Free Fabrication of Carbon Nanotube Based Ballistic CMOS Devices and Circuits , 2007 .

[30]  Yong-Bin Kim,et al.  Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability , 2010, Integr..

[31]  Yan Li,et al.  Almost perfectly symmetric SWCNT-based CMOS devices and scaling. , 2009, ACS nano.

[32]  J. Rogers,et al.  High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes. , 2007, Nature nanotechnology.

[33]  M. Lundstrom,et al.  Self-Aligned Ballistic Molecular Transistors and Electrically Parallel Nanotube Arrays , 2004, cond-mat/0406494.

[34]  Keivan Navi,et al.  Design and analysis of a high-performance CNFET-based Full Adder , 2012 .

[35]  Yan Li,et al.  Y-contacted high-performance n-type single-walled carbon nanotube field-effect transistors: scaling and comparison with Sc-contacted devices. , 2009, Nano letters.

[36]  Anantha Chandrakasan,et al.  Sub-threshold Design for Ultra Low-Power Systems , 2006, Series on Integrated Circuits and Systems.

[37]  Herbert Shea,et al.  Single- and multi-wall carbon nanotube field-effect transistors , 1998 .

[38]  Maki Suemitsu,et al.  Effects of the Hole Tunneling Barrier Width on the Electrical Characteristic in Silicon Quantum Dots Light-Emitting Diodes , 2011 .

[39]  Yusuke Murayama,et al.  Unravelling cerebellar pathways with high temporal precision targeting motor and extensive sensory and parietal networks , 2012, Nature Communications.

[40]  P. Avouris,et al.  Carbon Nanotube Inter- and Intramolecular Logic Gates , 2001 .

[41]  M. Dresselhaus,et al.  Physical properties of carbon nanotubes , 1998 .

[42]  V. T. Ingole,et al.  Design And Implementation Of 2 Bit Ternary ALU Slice , 2005 .

[43]  Kaushik Roy,et al.  Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[44]  S. Tans,et al.  Room-temperature transistor based on a single carbon nanotube , 1998, Nature.

[45]  Jörg Appenzeller,et al.  Carbon Nanotubes for High-Performance Electronics—Progress and Prospect , 2008, Proceedings of the IEEE.

[46]  Ali Zilouchian,et al.  Intelligent Control Systems Using Soft Computing Methodologies , 2000 .

[47]  H.-S. Philip Wong,et al.  Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[48]  Marc R. Nyden,et al.  Molecular Mechanics Calculations of the Thermodynamic Stabilities of Polymer–Carbon Nanotube Composites , 2006 .

[49]  Sheng Wang,et al.  CMOS-based carbon nanotube pass-transistor logic integrated circuits , 2012, Nature Communications.

[50]  Keivan Navi,et al.  Design and Evaluation of CNFET-Based Quaternary Circuits , 2012, Circuits, Systems, and Signal Processing.

[51]  Sheng Wang,et al.  Modularized construction of general integrated circuits on individual carbon nanotubes. , 2014, Nano letters.