An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology

A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90% is achieved way above the 40-50% usually seen in other networks on chips.

[1]  Hsin-Chou Chi,et al.  Design and implementation of a routing switch for on-chip interconnection networks , 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

[2]  Qin Wang,et al.  Simulation and Evaluation for SS Network on Chip architecture using OPNET , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[3]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[4]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[5]  P. Guerrier,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[6]  Manfred Glesner,et al.  A switch architecture and signal synchronization for GALS system-on-chips , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[7]  Ranga Vemuri,et al.  A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[8]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[9]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[10]  Maurizio Palesi,et al.  Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[11]  J. Oberg,et al.  Trading off power versus latency using GPLS clocking in 2D-mesh NoCs , 2005, International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005..

[12]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[13]  Srinivasan Murali,et al.  Routing Aware Switch Hardware Customization for Networks on Chips , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[14]  Kees G. W. Goossens,et al.  An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Axel Jantsch,et al.  Load distribution with the proximity congestion awareness in a network on chip , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[16]  A. Zitouni,et al.  New generic GALS NoC architectures with multiple QoS , 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

[17]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[18]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[19]  Fabien Clermidy,et al.  An asynchronous NOC architecture providing low latency service and its multi-level design framework , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[20]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[21]  Johnny Öberg,et al.  Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[22]  Jörg Henkel,et al.  On-chip networks: a scalable, communication-centric embedded system design paradigm , 2004, 17th International Conference on VLSI Design. Proceedings..

[23]  M NiLionel,et al.  The turn model for adaptive routing , 1992 .

[24]  Lionel M. Ni,et al.  The Turn Model for Adaptive Routing , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.

[25]  Y. Savaria,et al.  Design constraints of a hypertransport-compatible network-on-chip , 2004, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..