Integrated Inverse Class-F Silicon Power Amplifiers for High Power Efficiency at Microwave and mm-Wave

This paper presents two 2-stage inverse class-F power amplifiers (PAs) at 24 GHz and 38 GHz, integrated in 0.13 μm SiGe BiCMOS technology. The PAs are composed of an inverse class-F output stage proceeded by a class-AB driving amplifier. An inter-stage matching network between the driver and output stage delivers an optimal inter-stage power to the output stage with a maximum PAE in the driver amplifier. The output stage's load network based on multi-resonance LC resonators terminates harmonic impedance explicitly up to the third of the fundamental signal. By leveraging a native low capacitive reactance, the class-F-1 load network shapes a quasi-rectangular current waveform that effectively contains up to the fifth harmonic spectral component. A high impedance control is limited up to the second harmonic, shaping a half-sinusoid voltage peaking induced by DC, fundamental, and the second harmonic voltage spectra. The 24 GHz PA achieves 50% peak PAE, 16 dBm OP-1dB, 18 dBm Psat, and 19 dB saturated power gain with 2.3 V supply voltage at 24 GHz. The 24 GHz PA can maintain >45% PAE over 23.5-25.5 GHz and 1.5-2.4 V supply voltage range, manifesting a PAE robustness to the frequency and supply variations. For 38 GHz PA, measurements show 38.5% peak PAE, 15 dBm OP-1dB, 17 dBm Psat with 15 dB of saturated power gain at the OP-1dB point when 2.4 V supply voltage is applied. The 38 GHz PA can sustain >35% PAE over 36-39 GHz and 1.5-2.5 V supply variation. The PAs also are tested under the input of band-limited signals modulated by various modulation schemes including 8-PSK, QAM, 16-QAM, 64-QAM, and 128QAM, and test results are presented in this paper. The chip size is 0.95 × 0.6 mm2 for 24 GHz PA and 0.93 × 0.55 mm2 for 38 GHz PA, including all pads.

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