A scalable instruction buffer and align unit for xDSPcore

Increasing mask costs and decreasing feature sizes together with productivity demand have led to the trend of platform design. Software programmable embedded cores are used to provide the necessary flexibility in integrated systems. Facing increasing system complexity, single-issue digital signal processors (DSPs) have been replaced by cores providing the execution of several instructions in parallel. The most common programming model for multi-issue DSP core architectures is Very Long Instruction Word (VLIW) which is based on static scheduling, and enables minimization of the worst case execution time and reduces core complexity. The drawback of traditional VLIW is poor code density, which leads to high program memory requirements and, therefore, requires a large silicon area of the DSP subsystem. To overcome this problem without limiting the core performance, a scalable long instruction word (xLIW) is introduced. A special align unit is used for implementing the xLIW program memory interface. In this paper, the align unit and its main architectural feature, a scalable instruction buffer, is introduced in detail. xLIW is part of a project for a parameterized DSP core.

[1]  Jari Nurmi,et al.  xLIW - a scaleable long instruction word [DSP applications] , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[2]  V.S. Gierenz,et al.  A low power digital beamformer for handheld ultrasound systems , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[3]  Thomas D. Burd,et al.  The simulation and evaluation of dynamic voltage scaling algorithms , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[4]  Raimund Leitner,et al.  xLIW - a scaleable long instruction word. , 2003 .

[5]  Edward A. Lee,et al.  DSP Processor Fundamentals: Architectures and Features , 1997 .

[7]  Andreas Krall,et al.  VLIW operation refinement for reducing energy consumption , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

[8]  T.G. Noll,et al.  A flexible datapath generator for physical oriented design , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[9]  Edward A. Lee,et al.  DSP Processor Fundamentals , 1997 .

[10]  Péter Kacsuk,et al.  Advanced computer architectures - a design space approach , 1997, International computer science series.