Gate Driver Voltage Optimization for Multi-Mode Low Power DC-DC Conversion

In this paper we propose an optimization method for low power, high-efficiency DC-DC conversion. A detailed analysis of a multi-mode Step-Down (or Buck) converter losses is presented, allowing the comparison of the power MOS channel conduction losses with their gate-driving losses in order to find the optimum gate-driving voltage that maximizes the converter's efficiency. It is shown that the gate-voltage controller can be simplified to a unique voltage value applied below a determined output current, while still achieving efficiencies over 90% at output currents as low as 10 mA. Simulation results of a 600 mA, 2 MHz, Buck commercial converter, implemented in a 65 nm technology are presented validating the developed models and control methodology. A low power (<20 uW) simple adaptive timing circuit is proposed to efficiently implement the gate-voltage controller with low complexity, low die area (0.007 mm 2 ), and low quiescent current consumption (<2.4 uA).