Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity

A low power mapping algorithm for technology independent AND/XOR circuits is proposed. In this algorithm, the average power of the static mixed-polarity Reed—Muller (MPRM) circuits is minimized by generating a two-input gates circuit to optimize the switching active of nodes, and the power and area of MPRM circuits are estimated by using gates from a given library. On the basis of obtaining an optimal power MPRM circuit, the best mixed-polarity is found by combining an exhaustive searching method with polarity conversion algorithms. Our experiments over 18 benchmark circuits show that compared to the power optimization for fixed-polarity Reed-Muller circuits and AND/OR circuits, power saving is up to 44.22% and 60.09%, and area saving is up to 14.13% and 32.72%, respectively.

[1]  A. E. A. Almaini,et al.  Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion. , 2003 .

[2]  Ireneusz Brzozowski,et al.  A new approach to power estimation and reduction in CMOS digital circuits , 2008, Integr..

[3]  Hai Zhou,et al.  Optimal low power XOR gate decomposition , 2000, Proceedings 37th Design Automation Conference.

[4]  Chi-Ying Tsui,et al.  Technology Decomposition and Mapping Targeting Low Power Dissipation , 1993, 30th ACM/IEEE Design Automation Conference.

[5]  Tsutomu Sasao.  Easily Testable Realizations for Generalized Reed-Muller Expressions , 1997, IEEE Trans. Computers.

[6]  Xiao-ying Zhang,et al.  Efficient RM conversion algorithm for large multiple output functions , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[7]  A.E.A. Almaini,et al.  Minimization of incompletely specified mixed polarity reed muller functions using Genetic Algorithm , 2009, 2009 3rd International Conference on Signals, Circuits and Systems (SCS).

[8]  C. L. Liu,et al.  Low power logic synthesis for XOR based circuits , 1997, ICCAD 1997.

[9]  Wang Pengjun,et al.  Low Power Polarity Conversion Based on the Whole Annealing Genetic Algorithm , 2008 .

[10]  Neil Urquhart,et al.  Manipulation and optimisation techniques for Boolean logic , 2010, IET Comput. Digit. Tech..

[11]  Hai Zhou,et al.  An exact gate decomposition algorithm for low-power technology mapping , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[12]  Farid N. Najm,et al.  Early power estimation for VLSI circuits , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[14]  A. Kos,et al.  Calculation methods of new circuit activity measure for low power modeling , 2008, 2008 International Conference on Signals and Electronic Systems.