$1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS

Magnetization switching is confirmed for sub-3-ns pulses below <inline-formula> <tex-math notation="LaTeX">$100~\mu \text{A}$ </tex-math></inline-formula> in perpendicular magnetic tunnel junctions (MTJs) down to 16 nm in diameter. The magnetoresistance ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of −6 (10<sup>−6</sup>) are demonstrated. Read and write current margins, which are important device designs, are sufficiently large to avoid read disturbances. Moreover, <inline-formula> <tex-math notation="LaTeX">$1\times $ </tex-math></inline-formula>-to-<inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula>-nm MTJs have sufficient data retention for level-2 or level-3 cache requirements. Furthermore, the MTJ resistance remains stable after 10<sup>12</sup> write events. To the best of our knowledge, this is the first demonstration of <inline-formula> <tex-math notation="LaTeX">$1\times $ </tex-math></inline-formula>- to <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula>-nm MTJs supporting cache memory along with read–write current margins, fast read operations, low power consumption, sufficient retention, and high endurance.

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