Efficient Image Processing Algorithms on the Scan Line Array Processor

Develops efficient algorithms for low and intermediate level image processing on the scan line array processor, a SIMD machine consisting of a linear array of cells that processes images in a scan line fashion. For low level processing, the authors present algorithms for block DFT, block DCT, convolution, template matching, shrinking, and expanding which run in real-time. By real-time, the authors mean that, if the required processing is based on neighborhoods of size m/spl times/m, then the output lines are generated at a rate of O(m) operations per line and a latency of O(m) scan lines, which is the best that can be achieved on this model. The authors also develop an algorithm for median filtering which runs in almost real-time at a cost of O(m log m) time per scan line and a latency of [m/2] scan lines. For intermediate level processing, the authors present optimal algorithms for translation, histogram computation, scaling, and rotation. The authors also develop efficient algorithms for labelling the connected components and determining the convex hulls of multiple figures which run in O(n log n) and O(n log/sup 2/n) time, respectively. The latter algorithms are significantly simpler and easier to implement than those already reported in the literature for linear arrays. >

[1]  Gérard M. Baudet,et al.  Optimal Sorting Algorithms for Parallel Computers , 1978, IEEE Transactions on Computers.

[2]  Janak H. Patel,et al.  NETRA: an architecture for a large scale multiprocessor vision system , 1987 .

[3]  Joseph JáJá,et al.  Efficient Image Processing Algorithms on the Scan Line Array Processor , 1993, 1993 International Conference on Parallel Processing - ICPP'93.

[4]  David N. Chin,et al.  The Princeton Engine: a real-time video system simulator , 1988 .

[5]  E. L. Cloud,et al.  The geometric arithmetic parallel processor , 1988, Proceedings., 2nd Symposium on the Frontiers of Massively Parallel Computation.

[6]  R. M. Lea,et al.  ASP: a cost-effective parallel microcomputer , 1988, IEEE Micro.

[7]  Renato Stefanelli,et al.  PAPIA: Pyramidal architecture for parallel image analysis , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[8]  D. H. Schaefer,et al.  The GAM pyramid , 1987 .

[9]  Alan V. Oppenheim,et al.  Discrete-Time Signal Pro-cessing , 1989 .

[10]  I. V. Ramakrishnan,et al.  Modular Matrix Multiplication on a Linear Array , 1984, IEEE Trans. Computers.

[11]  Herb Taylor,et al.  The sarnoff engine: A massively parallel computer for high definition system simulation , 1994, J. VLSI Signal Process..

[12]  John R. Nickolls,et al.  The design of the MasPar MP-1: a cost effective massively parallel computer , 1990, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage.

[13]  Kenneth E. Batcher,et al.  Design of a Massively Parallel Processor , 1980, IEEE Transactions on Computers.

[14]  KSHITIJ A. DOSHI,et al.  Optimal Graph Algorithms on a Fixed-Size Linear Array , 1987, IEEE Transactions on Computers.

[15]  T. J. Fountain,et al.  The CLIP7A Image Processor , 1988, IEEE Trans. Pattern Anal. Mach. Intell..

[16]  Allan L. Fisher,et al.  Computing the Hough Transform on a Scan Line Array Processor (Image Processing) , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[17]  Anil K. Jain Fundamentals of Digital Image Processing , 2018, Control of Color Imaging Systems.

[18]  Allan L. Fisher Scan line array processors for image computation , 1986, ISCA 1986.

[19]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[20]  S. F. Reddaway DAP—a distributed array processor , 1973, ISCA 1973.