Multiplexer-based array multipliers

A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. Multiplier arrays for positive numbers and numbers in two's complement form based on the proposed technique are implemented. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and the interconnections of the cells are regular, well-suited for VLSI realization.

[1]  Shinji Nakamura.  Algorithms for Iterative Array Multiplication , 1986, IEEE Transactions on Computers.

[2]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[3]  O. L. Macsorley.  High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[4]  Yukihito Oowaki,et al.  A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology , 1987 .

[5]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[6]  Sudhir Ahuja,et al.  Effective Pipelining of Digital Systems , 1978, IEEE Transactions on Computers.

[7]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[8]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[9]  H. H. Guild.  Fully iterative fast array for binary multiplication and addition , 1969 .

[10]  A. D. Lopez,et al.  A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology , 1989 .

[11]  Shinji Nakamura,et al.  A Single Chip Parallel Multiplier by MOS Technology , 1988, IEEE Trans. Computers.

[12]  D. P. Burton,et al.  High-speed iterative multiplier , 1968 .

[13]  Hiroto Yasuura,et al.  High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.

[14]  Kai Hwang.  Global and Modular Two's Complement Cellular Array Multipliers , 1979, IEEE Trans. Computers.

[15]  Peter R. Cappello,et al.  A note on 'free accumulation' in VLSI filter architectures , 1985 .

[16]  R. Mori.  Suggestion for an i.c. fast parallel multiplier , 1969 .

[17]  M. A. Bayoumi,et al.  An efficient two's complement systolic multiplier for real-time digital signal processing , 1989 .

[18]  John G. McWhirter,et al.  Completely iterative, pipelined multiplier array suitable for VLSI , 1982 .

[19]  P. Csillag,et al.  Iterative logical network for parallel multiplication , 1968 .

[20]  M. Hatamian,et al.  Parallel bit-level pipelined VLSI designs for high-speed signal processing , 1987, Proceedings of the IEEE.