Compression in cache design
暂无分享,去创建一个
[1] M. Ekman,et al. A robust main-memory compression scheme , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[2] Jun Yang,et al. Frequent Value Locality and Value-Centric Data Cache Design , 2000, ASPLOS.
[3] Jang-Soo Lee,et al. Design and evaluation of a selective compressed memory system , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).
[4] Ronak Singhal,et al. Performance Analysis and Validation of the Intel Pentium 4 Processor on 90nm Technology , 2004 .
[5] Steven K. Reinhardt,et al. A unified compressed memory hierarchy , 2005, 11th International Symposium on High-Performance Computer Architecture.
[6] R. D. Valentine,et al. The Intel Pentium M processor: Microarchitecture and performance , 2003 .
[7] Steven K. Reinhardt,et al. A compressed memory hierarchy using an indirect index cache , 2004, WMPI '04.
[8] A. Agarwal,et al. Column-associative Caches: A Technique For Reducing The Miss Rate Of Direct-mapped Caches , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.
[9] David A. Wood,et al. Interactions Between Compression and Prefetching in Chip Multiprocessors , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.
[10] YangJun,et al. Frequent value locality and value-centric data cache design , 2000 .
[11] Jun Yang,et al. Frequent value compression in data caches , 2000, MICRO 33.
[12] Anant Agarwal,et al. Column-associative caches: a technique for reducing the miss rate of direct-mapped caches , 1993, ISCA '93.
[13] Mark Horowitz,et al. Cache performance of operating system and multiprogramming workloads , 1988, TOCS.
[14] David A. Wood,et al. Adaptive cache compression for high-performance processors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[15] Rajiv Gupta,et al. Enabling partial cache line prefetching through data compression , 2003, 2003 International Conference on Parallel Processing, 2003. Proceedings..
[16] Norman P. Jouppi,et al. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[17] Michael E. Wazlowski,et al. IBM Memory Expansion Technology (MXT) , 2001, IBM J. Res. Dev..
[18] Andreas Moshovos,et al. Dependence based prefetching for linked data structures , 1998, ASPLOS VIII.
[19] Yannis Smaragdakis,et al. The Case for Compressed Caching in Virtual Memory Systems , 1999, USENIX Annual Technical Conference, General Track.
[20] Jean-Loup Baer,et al. Reducing memory latency via non-blocking and prefetching caches , 1992, ASPLOS V.
[21] Todd C. Mowry,et al. Compiler-based prefetching for recursive data structures , 1996, ASPLOS VII.