A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code

Field programmable gate arrays (FPGAs) are readily affected by transient faults in the presence of radiation and other environmental hazards compared to application specific integrated circuits. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from soft errors arising from transient faults. In this letter, modified matrix code (MMC) is used for multibit error correction in FPGA-based systems, and dynamic partial reconfiguration is considered to reduce the reconfiguration time. We propose a first of its kind methodology for novel transient fault correction using MMC for FPGAs. To validate the design, the proposed method has been tested on a Kintex FPGA and its performance has been estimated in terms of hardware complexity, power consumption, overhead, and error correction efficiency.

[1]  Mehdi Baradaran Tahoori,et al.  Soft error mitigation for SRAM-based FPGAs , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[2]  Robert S. Swarz,et al.  Reliable Computer Systems: Design and Evaluation , 1992 .

[3]  Shyh-Jye Jou,et al.  An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications , 2008, IEEE Journal of Solid-State Circuits.

[4]  Udo Kebschull,et al.  Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[5]  Michael J. Wirthlin,et al.  FPGA partial reconfiguration via configuration scrubbing , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[6]  Fabio Salice,et al.  Convolutional Coding for SEU mitigation , 2008, 2008 13th European Test Symposium.

[7]  Kaushik Roy,et al.  Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Tomson Devis,et al.  ) BCH E NCODER AND D ECODER FOR WBAN USING LFSR AND BMA , 2014 .