Modelling a CNTFET with Undeposited CNT Defects

The Carbon NanoTube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. When designing and manufacturing a CNTFET, additional features such as pitch, number and position of the CNTs must be considered to assess its performance. One of the defect types that can occur when fabricating a CNTFET, is the absence of some CNTs following the deposition/growth step. As result of this type of defect, a CNTFET will show a change in operational characteristics because drain current, gate capacitance, and delay will be affected due to the lower number of CNTs present in the channel of the transistor. This paper presents a new model by which the drain current, the gate capacitance and the delay can be found when not all CNTs are deposited on the substrate. This results in an uneven CNT spacing, new equations are derived and shown to be applicable to both defective and defect-free CNTFETs. The proposed model has been implemented in MATLAB and has been extensively simulated to show that defects due to undeposited CNTs have a significant impact on the operation of a CNTFET. Degradation in performance is related to both the number and position of the defects.

[1]  H.-S. Philip Wong,et al.  Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Nishant Patil,et al.  Carbon Nanotube circuits in the presence of carbon nanotube density variations , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[3]  H. Wong,et al.  Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits , 2009, IEEE Transactions on Nanotechnology.

[4]  H. Wong,et al.  Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels , 2007, IEEE Transactions on Electron Devices.

[5]  H. Wong,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.

[6]  P. Umek,et al.  Selective etching of metallic single-wall carbon nanotubes with hydrogen plasma , 2005, Nanotechnology.

[7]  H. Dai,et al.  High performance n-type carbon nanotube field-effect transistors with chemically doped contacts. , 2004, Nano letters.

[8]  Nishant Patil,et al.  Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  M. Lundstrom,et al.  Self-Aligned Ballistic Molecular Transistors and Electrically Parallel Nanotube Arrays , 2004, cond-mat/0406494.

[10]  Jie Deng,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking , 2007, IEEE Transactions on Electron Devices.

[11]  P. Avouris,et al.  Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown , 2001, Science.

[12]  H. Wong,et al.  Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes , 2009, IEEE Transactions on Nanotechnology.