Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

SUMMARY Reconfigurable computing system is a class of parallel ar- chitecture with the ability of computing in hardware to increase performance, while remaining much of flexibility of a software solution. This ar- chitecture is particularly suitable for running regular and compute-intensive tasks, nevertheless, most compute-intensive tasks spend most of their run- ning time in nested loops. Polyhedron model is a powerful tool to give a reasonable transformation on such nested loops. In this paper, a num- ber of issues are addressed towards the goal of optimization of a ffi ne loop nests for reconfigurable cell array ( RCA ), such as approach to make the most use of processing elements ( PE ) while minimizing the communication volume by loop transformation in polyhedron model, determination of tilling form by the intra-statement dependence analysis and determination of tilling size by the tilling form and the RCA size. Experimental results on a number of kernels demonstrate the e ff ectiveness of the mapping optimization approaches developed. Compared with DFG-based optimization approach, the execution performances of 1-d jacobi and matrix multiplication are improved by 28% and 48 . 47%. Lastly, the run-time complexity is acceptable for the practical cases.