Permutation and phase independent Boolean comparison

Abstract This paper addresses the problem of checking the equivalence of two Boolean functions under arbitrary input permutations and/or input phase assignments. This problem has several applications in the synthesis and verification of combinational logic. It arises in the technology mapping stage of logic synthesis in finding a match from the cell library for parts of the technology independent circuit. In logic verification this is needed when the exact correspondence of inputs between the two circuits is not known. Exact solutions using exhaustive enumeration of the permutations and/or phase assignments are never a practical possibility, thus recourse is taken to heuristics that work well in practice. The approach presented in this paper computes a signature for each variable or phase of a variable that will help to establish correspondence of variables or phases of variables. The strength of the proposed approach depends on the ability to quickly derive a signature with minimum aliasing. Aliasing refers to two different variables or phases having the same signature, thus rendering this signature useless for the purpose of distinguishing between them. Experimental results on a large number of examples establish the efficacy of this approach.

[1]  Sharad Malik,et al.  Permutation and phase independent Boolean comparison , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[2]  Giovanni De Micheli,et al.  Technology mapping using Boolean matching and don't care sets , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[3]  Ulf Schlichtmann,et al.  Characterization of Boolean functions for rapid matching in EPGA technology mapping , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[4]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Cheng Chen,et al.  Restructuring binary decision diagrams based on functional equivalence , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[6]  Albert R. Wang,et al.  Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[7]  M. Marek-Sadowska,et al.  Verifying equivalence of functions with unknown input correspondence , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[8]  Masahiro Fujita,et al.  Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping , 1993, 30th ACM/IEEE Design Automation Conference.

[9]  Massoud Pedram,et al.  Boolean matching using binary decision diagrams with applications to logic synthesis and verification , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[10]  D. E. Long,et al.  Efficient Boolean function matching , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[11]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[12]  Jerry R. Burch,et al.  Efficient Boolean function matching , 1992, ICCAD.