The CDB/HCDB semiconductor wafer representation server

The chip database (CDB) and the hierarchical chip database (HCDB) and their uses in a wafer representation server are described. The server provides data types and methods for hierarchically representing the three-dimensional geometry and fields of a semiconductor wafer during process, device, and yield simulation. The basic database data types and the general attribute mechanism have been used to create database extensions. These extensions implement operations frequently used by process and device simulation models. The combination of the databases and extensions forms a CDB/HCDG server that greatly reduces the effort required to create new statistical process, device, and yield simulation models. Examples of using the server to implement new models are described. Performance data demonstrate that the server is fast enough for use by analytical models during statistical simulation of macrocells, and is able to meet the representation needs of numerical simulation. >

[1]  Steven G. Duvall,et al.  EASE--An Application-Based CAD System for Process Design , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Andrzej J. Strojwas,et al.  A semiconductor wafer representation database and its use in the PREDITOR proem editor and statistical simulator , 1991, 28th ACM/IEEE Design Automation Conference.

[3]  Sani R. Nassif,et al.  FABRICS II: A Statistically Based IC Fabrication Process Simulator , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  John K. Ousterhout,et al.  Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Robert W. Dutton,et al.  A manufacturing-oriented environment for synthesis of fabrication processes , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[6]  Chiakang Sung,et al.  A general simulator for VLSI lithography and etching processes: Part II—Application to deposition and etching , 1980, IEEE Transactions on Electron Devices.

[7]  Peter Lloyd,et al.  Technology CAD for competitive products , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Andrzej J. Strojwas,et al.  Numerical integral method for diffusion modeling , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  A.S. Wong,et al.  The intertool profile interchange format: a technology CAD environment approach [semiconductor technology] , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  A. J. Strojwas The process engineer's workbench , 1988 .

[11]  Robert W. Dutton,et al.  Intelligent Simulation for OPtimization of Fabrication Processes , 1990, Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits.

[12]  R.W. Dutton,et al.  New n-well fabrication techniques based on 2D process simulation , 1986, 1986 International Electron Devices Meeting.

[13]  Duane S. Boning,et al.  MASTIF (MIT Analysis and Simulation Tools for IC Fabrication) - A Workstation Approach to Fabrication Process Design, , 1985 .

[14]  M. L. Heytens,et al.  The Intertool Profile Interchange Format , 1990, Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits.

[15]  Robert W. Dutton,et al.  Verification of analytic point defect models using SUPREM-IV [dopant diffusion] , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  R.W. Dutton,et al.  A utility-based integrated process simulation system , 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

[17]  Michael L. Heytens,et al.  The intertool profile interchange format: an object-oriented approach [semiconductor technology CAD/CAM] , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Steven G. Duvall,et al.  An interchange format for process and device simulation , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  A. Neureuther,et al.  A general simulator for VLSI lithography and etching processes: Part I—Application to projection lithography , 1979, IEEE Transactions on Electron Devices.

[20]  Mark R. Simpson PRIDE: an integrated design environment for semiconductor device simulation , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  R.W. Dutton,et al.  VLSI Process modeling—SUPREM III , 1983, IEEE Transactions on Electron Devices.

[22]  K. Lee,et al.  SIMPL-2 (SIMulated Profiles from the Layout-Version 2) , 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.

[23]  M. Simpson,et al.  PRIDE: An Integrated Design Environment for Semiconductor Device Simulation , 1990, Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits.